Use of accelerometers to detect motor states in a seizure of rats with temporal lobe epilepsy. - Yu-Lin Wang; Sheng-Fu Liang; Fu-Zen Shaw; Alvin W. Y. Su; Yin-Lin Chen; Ssu-Yen Wu (BioCAS, 2012)

Detection of spontaneous temporal lobe epilepsy in rats by means of 1-axis accelerometor signal. - Yu-Lin Wang; Sheng-Fu Liang; Fu-Zen Shaw; Yu-Hsin Huang; Ssu-Yen Wu (ICICS, 2013)

A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. - Xin Si; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; Yen-Cheng Chiu; Wei-Chen Wei; Ssu-Yen Wu; Xiaoyu Sun 001; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; et al. (ISSCC, 2019)

A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS. - Ruiqi Guo; Yonggang Liu; Shixuan Zheng; Ssu-Yen Wu; Peng Ouyang; Win-San Khwa; Xi Chen; Jia-Jing Chen; Xiudong Li; Leibo Liu; Meng-Fan Chang; Shaojun Wei; et al. (VLSI Circuits, 2019)

13.4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices. - Tung-Cheng Chang; Yen-Cheng Chiu; Chun-Ying Lee; Je-Min Hung; Kuang-Tang Chang; Cheng-Xin Xue; Ssu-Yen Wu; Hui-Yao Kao; Peng Chen; Hsiao-Yu Huang; Shih-Hsih Teng; Meng-Fan Chang (ISSCC, 2020)

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Zhixiao Zhang; Syuan-Hao Sie; et al. (ISSCC, 2020)

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. - Xin Si; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Qiang Li 021; Meng-Fan Chang; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; et al. (IEEE J. Solid State Circuits, 2020)

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Yen-Lin Chung; William Shih; et al. (IEEE J. Solid State Circuits, 2021)

A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device. - Yen-Cheng Chiu; Tung-Cheng Chang; Chun-Ying Lee; Je-Min Hung; Kuang-Tang Chang; Cheng-Xin Xue; Ssu-Yen Wu; Hui-Yao Kao; Peng Chen; Hsiao-Yu Huang; Shih-Hsih Teng; Chieh-Pu Lo; et al. (IEEE J. Solid State Circuits, 2022)