A 23mW, 73dB dynamic range, 80MHz BW continuous-time delta-sigma modulator in 20nm CMOS. - Stacy Ho; Chi-Lun Lo; Zhiyu Ru; Jialin Zhao 001 (VLSIC, 2014)

15.1 An 85dB-DR 74.6dB-SNDR 50MHZ-BW CT MASH ΔΣ modulator in 28nm CMOS. - Do-Yeon Yoon; Stacy Ho; Hae-Seung Lee (ISSCC, 2015)

A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS. - Stacy Ho; Chi-Lun Lo; Jiayun Ru; Jialin Zhao 001 (IEEE J. Solid State Circuits, 2015)

A Continuous-Time Sturdy-MASH ΔΣ Modulator in 28 nm CMOS. - Do-Yeon Yoon; Stacy Ho; Hae-Seung Lee (IEEE J. Solid State Circuits, 2015)

Analog-digital partitioning and coupling in 3D-IC for RF applications. - Gilad Yahalom; Stacy Ho; Alice Wang; Uming Ko; Anantha P. Chandrakasan (3DIC, 2016)

A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR. - Tao He 001; Michael Ashburn; Stacy Ho; Yi Zhang 023; Gabor C. Temes (ISSCC, 2018)

A 20 kHz Bandwidth Resistive DAC with 135 dBA Dynamic Range and 125 dB THD. - Ayman Shabra; Padraig Cooney; Adalberto Cantoni; Joshua Bamford; Stacy Ho; Michael Ashburn (CICC, 2019)

A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation and Background Calibration Achieving 153.8dB FoM in 4nm CMOS. - Juzheng Liu; Ayman Shabra; Stacy Ho; Gabriele Manganaro; Mike Shuo-Wei Chen (VLSI Technology and Circuits, 2024)