Prototyping Efficient Interprocessor Communication Mechanisms. - Vassilis Papaefstathiou; Dionisios N. Pnevmatikatos; Manolis Marazakis; Giorgos Kalokairinos; Aggelos Ioannou; Michael Papamichael; Stamatis G. Kavadias; Giorgos Mihelogiannakis; Manolis Katevenis (ICSAMOS, 2007)

FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability. - George Kalokerinos; Vassilis Papaefstathiou; George Nikiforos; Stamatis G. Kavadias; Manolis Katevenis; Dionisios N. Pnevmatikatos; Xiaojun Yang (ICSAMOS, 2009)

On-chip communication and synchronization mechanisms with cache-integrated network interfaces. - Stamatis G. Kavadias; Manolis Katevenis; Michail Zampetakis; Dimitrios S. Nikolopoulos (Conf. Computing Frontiers, 2010)

Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface. - Christoforos Kachris; George Nikiforos; Stamatis G. Kavadias; Vassilis Papaefstathiou; Manolis Katevenis (ReConFig, 2010)

Explicit Communication and Synchronization in SARC. - Manolis Katevenis; Vassilis Papaefstathiou; Stamatis G. Kavadias; Dionisios N. Pnevmatikatos; Federico Silla; Dimitrios S. Nikolopoulos (IEEE Micro, 2010)

Fine-grain OpenMP runtime support with explicit communication hardware primitives. - Pranav Tendulkar; Vassilis Papaefstathiou; George Nikiforos; Stamatis G. Kavadias; Dimitrios S. Nikolopoulos; Manolis Katevenis (DATE, 2011)

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs. - Stamatis G. Kavadias; Manolis Katevenis; Michail Zampetakis; Dimitrios S. Nikolopoulos (Int. J. Parallel Program., 2012)

NP-SARC: Scalable network processing in the SARC multi-core FPGA platform. - Christoforos Kachris; George Nikiforos; Vassilis Papaefstathiou; Stamatis G. Kavadias; Manolis Katevenis (J. Syst. Archit., 2013)

Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability. - George Kalokerinos; Vassilis Papaefstathiou; George Nikiforos; Stamatis G. Kavadias; Xiaojun Yang; Dionisios N. Pnevmatikatos; Manolis Katevenis (Trans. High Perform. Embed. Archit. Compil., 2019)

Who Owns the Output? Bridging Law and Technology in LLMs Attribution. - Emanuele Mezzi; Asimina Mertzani; Michael P. Manis; Siyanna Lilova; Nicholas Vadivoulis; Stamatis G. Kavadias; Styliani Roussou; Rodayna Hmede (CoRR, 2025)