Design of Fast Self-Testing Checkers for a Class of Berger Codes. - Stanislaw J. Piestrak (IEEE Trans. Computers, 1987)

The minimal test set for sorting networks and the use of sorting networks in self-testing checkers for unordered codes. - Stanislaw J. Piestrak (FTCS, 1990)

Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes. - Stanislaw J. Piestrak (IEEE Trans. Computers, 1990)

Design of a Self-Testing Checker for Borden Code. - Stanislaw J. Piestrak (ICCD, 1991)

Efficient Encoding? Decoding Circuitry for Systematic Unidirectional Error-Detecting Codes. - Stanislaw J. Piestrak (Fault-Tolerant Computing Systems, 1991)

The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks. - Stanislaw J. Piestrak (IEEE Trans. Computers, 1993)

Design of TSC Code-Disjoint Inverter-Free PLA's for Separable Unordered Codes. - Stanislaw J. Piestrak (ICCD, 1994)

Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder Theorem. - Stanislaw J. Piestrak (ICCD, 1994)

Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders. - Stanislaw J. Piestrak (IEEE Trans. Computers, 1994)

Design of self-testing checkers for unidirectional error detecting codes. - Stanislaw J. Piestrak (1995)

Towards Totally Self-Checking Delay-Insensitive Systems. - Stanislaw J. Piestrak; Takashi Nanya (FTCS, 1995)

Self-Checking Design in Eastern Europe. - Stanislaw J. Piestrak (IEEE Des. Test Comput., 1996)

Design of Self-Testing Checkers for Borden Codes. - Stanislaw J. Piestrak (IEEE Trans. Computers, 1996)

Design of minimal-level PLA self-testing checkers for m-out-of-n codes. - Stanislaw J. Piestrak (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes. - Stanislaw J. Piestrak (DFT, 1997)

Membership Test Logic for Delay-Insensitive Codes. - Stanislaw J. Piestrak (ASYNC, 1998)

VLSI implementation and complexity comparison of residue generators modulo 3. - Stanislaw J. Piestrak; Fabrice Pedron; Olivier Sentieys (EUSIPCO, 1998)

Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters. - Stanislaw J. Piestrak (J. Electron. Test., 1998)

Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits. - Jerzy W. Greblicki; Stanislaw J. Piestrak (EDCC, 1999)

Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes. - Stanislaw J. Piestrak; Abbas Dandache; Fabrice Monteiro (DFT, 2001)

On the Design of Self-Testing Checkers for Modified Berger Codes. - Stanislaw J. Piestrak; Dimitris Bakalis; Xrysovalantis Kavousianos (IOLTW, 2001)

Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage. - Stanislaw J. Piestrak (DFT, 2002)

Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes. - Stanislaw J. Piestrak (IEEE Trans. Computers, 2002)

Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning'. - Stanislaw J. Piestrak (IEEE Trans. Computers, 2002)

Designing fault-secure parallel encoders for systematic linear error correcting codes. - Stanislaw J. Piestrak; Abbas Dandache; Fabrice Monteiro (IEEE Trans. Reliab., 2003)

Modeling of Transients Caused by a Laser Attack on Smart Cards. - Damien Leroy; Stanislaw J. Piestrak; Fabrice Monteiro; Abbas Dandache (IOLTS, 2005)

Characterizing Laser-Induced Pulses in ICs: Methodology and Results. - Damien Leroy; Stanislaw J. Piestrak; Fabrice Monteiro; Abbas Dandache; Stéphane Rossignol; Pascal Moitrel (IOLTS, 2006)

Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes. - Fabrice Monteiro; Stanislaw J. Piestrak; Houssein Jaber; Abbas Dandache (IOLTS, 2007)

Exploiting residue number system for power-efficient digital signal processing in embedded processors. - Rooju Chokshi; Krzysztof S. Berezowski; Aviral Shrivastava; Stanislaw J. Piestrak (CASES, 2009)

Design of parallel fault-secure encoders for systematic cyclic block transmission codes. - Houssein Jaber; Fabrice Monteiro; Stanislaw J. Piestrak; Abbas Dandache (Microelectron. J., 2009)

On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels. - Stanislaw J. Piestrak (DSD, 2010)

Design of cost-efficient multipliers modulo 2a-1. - Stanislaw J. Piestrak (ISCAS, 2010)

Design of a fault-tolerant coarse-grained. - Syed M. A. H. Jafri; Stanislaw J. Piestrak; Olivier Sentieys; Sébastien Pillement (ISQED, 2010)

Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication". - Stanislaw J. Piestrak; Sébastien Pillement; Olivier Sentieys (IEEE Commun. Lett., 2010)

Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication. - Stanislaw J. Piestrak; Sébastien Pillement; Olivier Sentieys (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Error recovery technique for coarse-grained reconfigurable architectures. - Muhammad Moazam Azeem; Stanislaw J. Piestrak; Olivier Sentieys; Sébastien Pillement (DDECS, 2011)

Design of multi-residue generators using shared logic. - Stanislaw J. Piestrak (ISCAS, 2011)

Fast and energy-efficient constant-coefficient FIR filters using residue number system. - Piotr Patronik; Krzysztof S. Berezowski; Stanislaw J. Piestrak; Janusz Biernat; Aviral Shrivastava (ISLPED, 2011)

Design of an RNS reverse converter for a new five-moduli special set. - Piotr Patronik; Krzysztof S. Berezowski; Janusz Biernat; Stanislaw J. Piestrak; Aviral Shrivastava (ACM Great Lakes Symposium on VLSI, 2012)

Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs. - Syed M. A. H. Jafri; Stanislaw J. Piestrak; Kolin Paul; Ahmed Hemani; Juha Plosila; Hannu Tenhunen (DSD, 2013)

Implementation and evaluation of configuration scrubbing on CGRAs: A case study. - Syed M. A. H. Jafri; Stanislaw J. Piestrak; Ahmed Hemani; Kolin Paul; Juha Plosila; Hannu Tenhunen (ISSoC, 2013)

Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor. - Hung-Manh Pham; Sébastien Pillement; Stanislaw J. Piestrak (IEEE Trans. Computers, 2013)

Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs. - B. Chagun Basha; Stanislaw J. Piestrak; Sébastien Pillement (ARC, 2014)

Design of Fault-Secure Transposed FIR Filters Protected Using Residue Codes. - Stanislaw J. Piestrak; Piotr Patronik (DSD, 2014)

Private reliability environments for efficient fault-tolerance in CGRAs. - Syed M. A. H. Jafri; Stanislaw J. Piestrak; Ahmed Hemani; Kolin Paul; Juha Plosila; Hannu Tenhunen (Des. Autom. Embed. Syst., 2014)

Design of the coarse-grained reconfigurable architecture DART with on-line error detection. - Syed M. A. H. Jafri; Stanislaw J. Piestrak; Olivier Sentieys; Sébastien Pillement (Microprocess. Microsystems, 2014)

Design of Reverse Converters for General RNS Moduli Sets {2k, 2n-1, 2n+1, 2n+1-1} and {2k, 2n-1, 2n+1, 2n-1-1} (n even). - Piotr Patronik; Stanislaw J. Piestrak (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Design of Reverse Converters for the New RNS Moduli Set {2n+1, 2n-1, 2n, 2n-1+1} (n odd). - Piotr Patronik; Stanislaw J. Piestrak (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Fault-aware configurable logic block for reliable reconfigurable FPGAs. - B. Chagun Basha; Sébastien Pillement; Stanislaw J. Piestrak (ISCAS, 2015)

Fault-tolerant implementation of direct FIR filters protected using residue codes. - Stanislaw J. Piestrak; Piotr Patronik (NORCAS, 2015)

A note on RNS architectures for the implementation of the diagonal function. - Stanislaw J. Piestrak (Inf. Process. Lett., 2015)

Design of a low-power RNS-enhanced arithmetic unit. - Piotr Patronik; Stanislaw J. Piestrak (LASCAS, 2016)

Design of residue generators with CLA/compressor trees and multi-bit EAC. - Piotr Patronik; Stanislaw J. Piestrak (LASCAS, 2017)

Design of Reverse Converters for a New Flexible RNS Five-Moduli Set {2k, 2n-1, 2n+1, 2n+1-1, 2n-1-1} (n Even). - Piotr Patronik; Stanislaw J. Piestrak (Circuits Syst. Signal Process., 2017)

Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units. - Piotr Patronik; Stanislaw J. Piestrak (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Correction to: Design of Reverse Converters for a New Flexible RNS Five-Moduli Set {2k, 2n-1, 2n+1, 2n+1-1, 2n-1-1} (n Even). - Piotr Patronik; Stanislaw J. Piestrak (Circuits Syst. Signal Process., 2018)

Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels. - Piotr Patronik; Stanislaw J. Piestrak (J. Signal Process. Syst., 2018)

Design of reverse converters for the general RNS 3-moduli set {2k, 2n - 1, 2n + 1}. - Piotr Patronik; Stanislaw J. Piestrak (EURASIP J. Adv. Signal Process., 2023)

Efficient Implementations of Residue Generators Mod 2n + 1 Providing Diminished-1 Representation. - Stanislaw J. Piestrak; Piotr Patronik (CoRR, 2025)