PC-CUBE, a personal computer based hypercube. - Alex Ho; Geoffrey C. Fox; David W. Walker; Scott Snyder; Douglas Chang; Stanley Chen; Matt Breaden; Terry Cole (C³P, 1988)

A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS. - Jafar Savoj; Kenny C.-H. Hsieh; Parag Upadhyaya; Fu-Tai An; Ade Bekele; Stanley Chen; Xuewen Jiang; Kang Wei Lai; Chi Fung Poon; Aman Sewani; Didem Turker; Karthik Venna; et al. (VLSIC, 2012)

2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS. - Jun-Chau Chien; Parag Upadhyaya; Howard Jung; Stanley Chen; Wayne Fang; Ali M. Niknejad; Jafar Savoj; Ken Chang (ISSCC, 2014)

3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS. - Parag Upadhyaya; Jafar Savoj; Fu-Tai An; Ade Bekele; Anup P. Jose; Bruce Xu; Zhaoyin Daniel Wu; Didem Turker; Hesam Amir Aslanzadeh; Hiva Hedayati; Jay Im; Siok-Wei Lim; et al. (ISSCC, 2015)

A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology. - Parag Upadhyaya; Ade Bekele; Didem Turker Melek; Haibing Zhao; Jay Im; Junho Cho; Kee Hian Tan; Scott McLeod; Stanley Chen; Wenfeng Zhang; Yohan Frans; Ken Chang (VLSI Circuits, 2016)

6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET. - Jay Im; Dave Freitas; Arianne Roldan; Ronan Casey; Stanley Chen; Adam Chou; Tim Cronin; Kevin Geary; Scott McLeod; Lei Zhou; Ian Zhuang; Jaeduk Han; et al. (ISSCC, 2017)

A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET. - Jay Im; Dave Freitas; Arianne Roldan; Ronan Casey; Stanley Chen; Adam Chou; Tim Cronin; Kevin Geary; Scott McLeod; Lei Zhou; Ian Zhuang; Jaeduk Han; et al. (IEEE J. Solid State Circuits, 2017)

A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET. - Stanley Chen; Lei Zhou; Ian Zhuang; Jay Im; Didem Turker Melek; Jinyung Namkoong; Mayank Raj; Jaewook Shin; Yohan Frans; Ken Chang (ISSCC, 2018)

A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET. - Jay Im; Stanley Chen; Dave Freitas; Adam Chou; Lei Zhou; Ian Zhuang; Tim Cronin; David Mahashin; Winson Lin; Kok Lim Chan; Hongyuan Zhao; Kee Hian Tan; et al. (VLSI Circuits, 2018)

6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET. - Jay Im; Kevin Zheng; Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (ISSCC, 2020)

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET. - Jay Im; Kevin Zheng; Chuen-Huei Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (IEEE J. Solid State Circuits, 2021)