Abax: 2D/3D legaliser supporting look-ahead legalisation and blockage strategies. - Nikolaos Sketopoulos; Christos P. Sotiriou; Stavros Simoglou (DATE, 2018)

Timing Errors in STA-based Gate-Level Simulation. - Stavros Simoglou; Christos P. Sotiriou; Nikolaos Blias (ASYNC, 2020)

STA for Mixed Cyclic, Acyclic Circuits. - Stavros Simoglou; Christos P. Sotiriou; Dimitris Valiantzas; Nikolaos Sketopoulos (ISVLSI, 2020)

Graph-based STA for asynchronous controllers. - Stavros Simoglou; Nikolaos Xiromeritis; Christos P. Sotiriou; Nikolaos Sketopoulos (Integr., 2020)

Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits. - Stavros Simoglou; Christos P. Sotiriou; Nikolaos Blias (DFT, 2021)

Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance. - Dimitrios Garyfallou; Stavros Simoglou; Nikolaos Sketopoulos; Charalampos Antoniadis; Christos P. Sotiriou; Nestor E. Evmorfopoulos; George I. Stamoulis (IEEE Trans. Very Large Scale Integr. Syst., 2021)

RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening. - Christos Georgakidis; Stavros Simoglou; Christos P. Sotiriou (DFT, 2022)

Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows. - Nikolaos Blias; Iordanis Lilitsis; Stavros Simoglou; Evangelos Bakas; Christos P. Sotiriou (VLSI-SoC, 2022)

Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis. - Christos Georgakidis; Dimitris Valiantzas; Stavros Simoglou; Iordanis Lilitsis; Nikolaos Chatzivangelis; Ilias Golfos; Marko S. Andjelkovic; Christos P. Sotiriou; Milos Krstic (DFT, 2023)

Full Stage Delay Calculation Using Full Waveform Propagation and Standard Library CCS Model. - Stavros Simoglou; Iordanis Lilitsis; Nikolaos Blias; Christos P. Sotiriou (ISQED, 2024)