Pushing the speed limits of SiGe: C HBTs up to 0.5 Terahertz. - Stefaan Decoutere; Stefaan Van Huylenbroeck; Bernd Heinemann; Alexander Fox; Pascal Chevalier 002; Alain Chantre; Thomas F. Meister; Klaus Aufinger; Michael Schröter (CICC, 2009)

Methodology for extracting the characteristic capacitances of a power MOSFET transistor, using conventional on-wafer testing techniques. - Christoph Kerner; Ivan Ciofi; Thomas Chiarella; Stefaan Van Huylenbroeck (ESSDERC, 2012)

Cu seeding using electroless deposition on Ru liner for high aspect ratio through-Si vias. - Fumihiro Inoue; Harold Philipsen; Marleen H. van der Veen; Kevin Vandersmissen; Stefaan Van Huylenbroeck; Herbert Struyf; Tetsu Tanaka (3DIC, 2014)

Reliability challenges for barrier/liner system in high aspect ratio through silicon vias. - Yunlong Li; Stefaan Van Huylenbroeck; Els Van Besien; Xiaoping Shi; Chen Wu; Michele Stucchi; Gerald Beyer; Eric Beyne; Ingrid De Wolf; Kristof Croes (Microelectron. Reliab., 2014)

Impact of oxide liner properties on TSV Cu pumping and TSV stress. - Joke De Messemaeker; O. Varela Pedreira; A. Moussa; Nabi Nabiollahi; Kris Vanstreels; Stefaan Van Huylenbroeck; Harold Philipsen; Patrick Verdonck; Bart Vandevelde; Ingrid De Wolf; Eric Beyne; Kris Croes (IRPS, 2015)

Active-lite interposer for 2.5 & 3D integration. - Geert Hellings; Mirko Scholz; Mikael Detalle; Dimitrios Velenis; Muriel de Potter de ten Broeck; C. Roda Neve; Y. Li; Stefaan Van Huylenbroeck; Shih-Hung Chen; Erik Jan Marinissen; Antonio La Manna; Geert Van der Plas; et al. (VLSIC, 2015)

Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module. - Stefaan Van Huylenbroeck; Yunlong Li; Michele Stucchi; Lieve Bogaerts; Joeri De Vos; Gerald Beyer; Eric Beyne; Mohand Brouri; Praveen Nalla; Sanjay Gopinath; Matthew Thorum; Joe Richardson; et al. (3DIC, 2016)

TSV process-induced MOS reliability degradation. - Yunlong Li; Michele Stucchi; Stefaan Van Huylenbroeck; Geert Van der Plas; Gerald Beyer; Eric Beyne; Kristof Croes (IRPS, 2018)

Process Complexity and Cost Considerations of Multi-Layer Die Stacks. - Dimitrios Velenis; Joeri De Vos; Soon-Wook Kim; Jaber Derakhshandeh; Pieter Bex; Giovanni Capuz; Samuel Suhard; Kenneth June Rebibis; Stefaan Van Huylenbroeck; Erik Jan Marinissen; Alain Phommahaxay; Andy Miller; et al. (3DIC, 2019)