Embedded SRAM design in deep deep submicron technologies. - Wim Dehaene; Stefan Cosemans; Anselme Vignon; F. Catthoora; Peter Geens (ESSCIRC, 2007)

A Low-Power Embedded SRAM for Wireless Applications. - Stefan Cosemans; Wim Dehaene; Francky Catthoor (IEEE J. Solid State Circuits, 2007)

A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability. - Stefan Cosemans; Wim Dehaene; Francky Catthoor (ESSCIRC, 2008)

A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context. - Anselme Vignon; Stefan Cosemans; Wim Dehaene; Pol Marchal; Marco Facchini (DATE, 2009)

A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers. - Stefan Cosemans; Wim Dehaene; Francky Catthoor (IEEE J. Solid State Circuits, 2009)

A 4.4pJ/access 80MHz, 2K word \

8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes. - Vibhu Sharma; Stefan Cosemans; Maryam Ashouei; Jos Huisken; Francky Catthoor; Wim Dehaene (ESSCIRC, 2011)

A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh. - Anselme Vignon; Stefan Cosemans; Wim Dehaene (ESSCIRC, 2011)

A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy. - Vibhu Sharma; Stefan Cosemans; Maryam Ashouei; Jos Huisken; Francky Catthoor; Wim Dehaene (IEEE J. Solid State Circuits, 2011)

Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM. - Vibhu Sharma; Stefan Cosemans; Maryam Ashouei; Jos Huisken; Francky Catthoor; Wim Dehaene (DATE, 2012)

Analysis of the effect of cell parameters on the maximum RRAM array size considering both read and write. - Leqi Zhang; Stefan Cosemans; Dirk J. Wouters; Guido Groeseneken; Malgorzata Jurczak (ESSDERC, 2012)

A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link. - Bram Rooseleer; Stefan Cosemans; Wim Dehaene (IEEE J. Solid State Circuits, 2012)

Ultra Low-Energy SRAM Design for Smart Ubiquitous Sensors. - Vibhu Sharma; Stefan Cosemans; Maryam Ashouei; Jos Huisken; Francky Catthoor; Wim Dehaene (IEEE Micro, 2012)

Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier. - Innocent Agbo; Mottaqiallah Taouil; Said Hamdioui; Stefan Cosemans; Pieter Weckx; Praveen Raghavan; Francky Catthoor (DTIS, 2015)

BTI analysis of SRAM write driver. - Innocent Agbo; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Francky Catthoor (IDT, 2015)

NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs. - Azam Seyedi; Vasileios Karakostas; Stefan Cosemans; Adrián Cristal; Mario Nemirovsky; Osman S. Unsal (NANOARCH, 2015)

STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance. - Raf Appeltans; Stefan Cosemans; Praveen Raghavan; Diederik Verkest; Liesbet Van der Perre; Wim Dehaene (NVMSA, 2015)

Comparative BTI analysis for various sense amplifier designs. - Innocent Agbo; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Praveen Raghavan; Francky Catthoor (DDECS, 2016)

Read path degradation analysis in SRAM. - Innocent Agbo; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Francky Catthoor; Wim Dehaene (ETS, 2016)

Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability. - Innocent Agbo; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Praveen Raghavan; Francky Catthoor; Wim Dehaene (ISVLSI, 2016)

Mitigation of sense amplifier degradation using input switching. - Daniel Kraak; Innocent Agbo; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Francky Catthoor; Wim Dehaene (DATE, 2017)

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7. - Mohit Kumar Gupta 001; Pieter Weckx; Stefan Cosemans; Pieter Schuddinck; Rogier Baert; Dmitry Yakimets; Doyoung Jang; Yasser Sherazi; Praveen Raghavan; Alessio Spessot; Anda Mocuta; Wim Dehaene (ESSDERC, 2017)

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7. - Mohit Kumar Gupta 001; Pieter Weckx; Stefan Cosemans; Pieter Schuddinck; Rogier Baert; Doyoung Jang; Yasser Sherazi; Praveen Raghavan; Alessio Spessot; Anda Mocuta; Wim Dehaene (ICICDT, 2017)

Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads. - Daniel Kraak; Mottaqiallah Taouil; Innocent Agbo; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Francky Catthoor (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Degradation analysis of high performance 14nm FinFET SRAM. - Daniel Kraak; Innocent Agbo; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Francky Catthoor (DATE, 2018)

Study of breakdown in STT-MRAM using ramped voltage stress and all-in-one maximum likelihood fit. - Simon Van Beek; Philippe Roussel; Barry J. O'Sullivan; Robin Degraeve; Stefan Cosemans; Dimitri Linten; Gouri Sankar Kar (ESSDERC, 2018)

Analytic variability study of inference accuracy in RRAM arrays with a binary tree winner-take-all circuit for neuromorphic applications. - Jonas Doevenspeck; Robin Degraeve; Stefan Cosemans; Philippe Roussel; Bram-Ernst Verhoef; Rudy Lauwereins; Wim Dehaene (ESSDERC, 2018)

Impact and mitigation of SRAM read path aging. - Innocent Agbo; Mottaqiallah Taouil; Daniel Kraak; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Francky Catthoor; Wim Dehaene (Microelectron. Reliab., 2018)

Methodology for Application-Dependent Degradation Analysis of Memory Timing. - Daniel Kraak; Innocent Agbo; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Francky Catthoor (DATE, 2019)

Hardware-Based Aging Mitigation Scheme for Memory Address Decoder. - Daniel Kraak; Innocent Agbo; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Francky Catthoor (ETS, 2019)

FQ-Conv: Fully Quantized Convolution for Efficient and Accurate Inference. - Bram-Ernst Verhoef; Nathan Laubeuf; Stefan Cosemans; Peter Debacker; Ioannis A. Papistas; Arindam Mallik; Diederik Verkest (CoRR, 2019)

Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM. - Daniel Kraak; Mottaqiallah Taouil; Innocent Agbo; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Francky Catthoor (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Mitigation of Sense Amplifier Degradation Using Skewed Design. - Daniel Kraak; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Francky Catthoor (DATE, 2020)

eSRAM Reliability: Why is it still not optimally solved? - Daniël Kraak; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Francky Catthoor (DTIS, 2020)

A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration. - Ioannis A. Papistas; Stefan Cosemans; Bram Rooseleer; Jonas Doevenspeck; Myung Hee Na; Arindam Mallik; Peter Debacker; Diederik Verkest (CICC, 2021)

STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application. - Sidharth Rao; Woojin Kim; Simon Van Beek; Shreya Kundu; Manu Perumkunnil; Stefan Cosemans; Farrukh Yasin; Sebastien Couet; Robert Carpenter; Barry J. O'Sullivan; Shamin H. Sharifi; N. Jossart; et al. (IMW, 2021)

Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution. - Simon Van Beek; Siddharth Rao; Shreya Kundu; Woojin Kim; Barry J. O'Sullivan; Stefan Cosemans; Farrukh Yasin; Robert Carpenter; Sebastien Couet; Shamin H. Sharifi; Nico Jossart; Davide Crotti; et al. (IRPS, 2021)

Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration. - Debjyoti Bhattacharjee; Nathan Laubeuf; Stefan Cosemans; Ioannis A. Papistas; Arindam Mallik; Peter Debacker; Myung Hee Na; Diederik Verkest (ISCAS, 2021)

Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing. - Michele Caselli; Ioannis A. Papistas; Stefan Cosemans; Arindam Mallik; Peter Debacker; Diederik Verkest (NEWCAS, 2021)

DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. - Kodai Ueyoshi; Ioannis A. Papistas; Pouya Houshmand; Giuseppe Maria Sarda; Vikram Jain; Man Shi; Qilin Zheng; Juan Sebastian Piedrahita Giraldo; Peter Vrancx; Jonas Doevenspeck; Debjyoti Bhattacharjee; Stefan Cosemans; et al. (ISSCC, 2022)

Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators. - Hongwu Jiang; Wantong Li; Shanshi Huang; Stefan Cosemans; Francky Catthoor; Shimeng Yu (IEEE Des. Test, 2022)

Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration. - Nathan Laubeuf; Jonas Doevenspeck; Ioannis A. Papistas; Michele Caselli; Stefan Cosemans; Peter Vrancx; Debjyoti Bhattacharjee; Arindam Mallik; Peter Debacker; Diederik Verkest; Francky Catthoor; Rudy Lauwereins (ACM Trans. Design Autom. Electr. Syst., 2022)

A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W. - Mohit Gupta 004; Stefan Cosemans; Peter Debacker; Wim Dehaene (ESSCIRC, 2023)

Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays. - Subhali Subhechha; Stefan Cosemans; Attilio Belmonte; Nouredine Rassoul; Shamin Houshmand Sharifi; Peter Debacker; Diederik Verkest; Romain Delhougne; Gouri Sankar Kar (IMW, 2023)

Evaluating the Effects of FeFET Device Variability on Charge Sharing Based AiMC Accelerator. - Swatilekha Majumdar; Stefan Cosemans; Arindam Mallik; Peter Debacker; Francky Catthoor; Jan Van Houdt (ISCAS, 2023)

11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge. - Pascal Alexander Hager; Bert Moons; Stefan Cosemans; Ioannis A. Papistas; Bram Rooseleer; Jeroen Van Loon; Roel Uytterhoeven; Florian Zaruba; Spyridoula Koumousi; Milos Stanisavljevic; Stefan Mach; Sebastiaan Mutsaards; et al. (ISSCC, 2024)

Extremely Scaled Perpendicular SOT-MRAM Array Integration on 300mm Wafer. - Farrukh Yasin; A. Palomino; A. Kumar; Valerio Pica; Simon Van Beek; Giacomo Talmelli; Van D. Nguyen; Stefan Cosemans; D. Crotti; Kurt Wostyn; Gouri Sankar Kar; Sebastien Couet (VLSI Technology and Circuits, 2024)