First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP. - Gayle Murdoch; Matin O'Toole; Giulio Marti; Ankit Pokhrel; Diana Tsvetanova; Stefan Decoster; Shreya Kundu; Yusuke Oniki; Arame Thiam; Quoc Toan Le; Olalla Varela Pedreira; Alicja Lesniewska; et al. (VLSI Technology and Circuits, 2022)

Towards low damage and fab-compatible top-contacts in MX2 transistors using a combined synchronous pulse atomic layer etch and wet-chemical etch approach. - Shreya Kundu; D. H. van Doip; Tom Schram; Quentin Smets; S. Banerjee; Benjamin Groven; Daire Cott; Stefan Decoster; P. Bezard; F. Lazzarino; K. Banerjee; Souvik Ghosh 001; et al. (VLSI Technology and Circuits, 2023)

Mitigating Line-Break Defectivity with a Sandwiched TiN or W Layer for Metal Pitch 18 NM Aspect Ratio 6 Semi-Damascene Interconnects. - Anshul Gupta; Shreya Kundu; Stefan Decoster; K. Sah; G. Delie; B. Truijen; Davide Tierno; Giulio Marti; O. Varela Pedreira; B. Kenens; Y. Hermans; C. Adelmann; et al. (VLSI Technology and Circuits, 2024)