A 14 bit self-calibrating charge redistribution SAR ADC. - Stefan Hänzsche; Stephan Henker; René Schüffny; Thomas Reichel; Matthias Garzarolli (ISCAS, 2012)

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS. - Dennis Walter; Sebastian Höppner; Holger Eisenreich; Georg Ellguth; Stephan Henker; Stefan Hänzsche; René Schüffny; Markus Winter 002; Gerhard P. Fettweis (ISSCC, 2012)

A 32 GBit/s communication SoC for a waferscale neuromorphic system. - Stefan Scholze; Holger Eisenreich; Sebastian Höppner; Georg Ellguth; Stephan Henker; Mario Ander; Stefan Hänzsche; Johannes Partzsch; Christian Mayr 001; René Schüffny (Integr., 2012)

Behavioral model of a continuous current integrator with time discrete feedback and sampling. - Johannes Gorner; Johannes Uhlig; Stefan Hänzsche; René Schüffny (ECCTD, 2013)

Analysis of a charge redistribution SAR ADC with partially thermometer coded DAC. - Stefan Hänzsche; René Schüffny (ECCTD, 2013)

Rapid prototyping of higher order incremental ΣΔ-ADC topologies and NTFs. - Johannes Uhlig; Stefan Hänzsche; René Schüffny; Thomas Reichel; Lars Gopfert; Valeri Razhenikov (ICECS, 2013)

Hybrid incremental-ΣΔ-ADC for ambient light sensing applications. - Johannes Uhlig; Stefan Hänzsche; Johannes Gorner; René Schüffny; Thomas Reichel; Lars Gopfert (ISCAS, 2013)

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology. - Sebastian Höppner; Stefan Hänzsche; Georg Ellguth; Dennis Walter; Holger Eisenreich; René Schüffny (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A compact on-chip IR-drop measurement system in 28 nm CMOS technology. - Sebastian Dietel; Sebastian Höppner; Holger Eisenreich; Georg Ellguth; Stefan Hänzsche; Stephan Henker; René Schüffny; Tim Brauninger; Ulrich Fiedler (ISCAS, 2014)

A 10 bit 16 MS/s redundant SAR ADC with flexible window function for a digitally controlled DC-DC converter in 28 nm CMOS. - Stefan Hänzsche; Sebastian Höppner; René Schüffny (NORCHIP, 2014)

Switched-Capacitor Realization of Presynaptic Short-Term-Plasticity and Stop-Learning Synapses in 28 nm CMOS. - Marko Noack; Johannes Partzsch; Christian Mayr 001; Stefan Hänzsche; Stefan Scholze; Sebastian Höppner; Georg Ellguth; René Schüffny (CoRR, 2014)

A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology. - Stefan Hänzsche; Sebastian Höppner; Georg Ellguth; René Schüffny (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

An all-digital PWM generator with 62.5ps resolution in 28nm CMOS technology. - Sebastian Höppner; Stefan Hänzsche; Stefan Scholze; René Schüffny (ISCAS, 2015)

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS. - Sebastian Höppner; Dennis Walter; Thomas Hocker; Stephan Henker; Stefan Hänzsche; Daniel Sausner; Georg Ellguth; Jens-Uwe Schluessler; Holger Eisenreich; René Schüffny (IEEE J. Solid State Circuits, 2015)

A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits. - Christian Mayr 001; Johannes Partzsch; Marko Noack; Stefan Hänzsche; Stefan Scholze; Sebastian Höppner; Georg Ellguth; René Schüffny (IEEE Trans. Biomed. Circuits Syst., 2016)

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications. - Sebastian Haas; Tobias Seifert; Benedikt Nöthen; Stefan Scholze; Sebastian Höppner; Andreas Dixius; Esther Pérez Adeva; Thomas R. Augustin; Friedrich Pauls; Sadia Moriam; Mattis Hasler; Erik Fischer; et al. (DAC, 2017)

Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS. - Florian Protze; Martin Kreißig; Frank Ellinger; Sebastian Höppner; Stephan Hartmann 002; Stefan Hänzsche; Stefan Scholze; Georg Ellguth; Christian Mayr 001 (VLSI-SoC, 2019)

Mean Field Approach for Configuring Population Dynamics on a Biohybrid Neuromorphic System. - Johannes Partzsch; Christian Mayr 001; Massimiliano Giulioni; Marko Noack; Stefan Hänzsche; Stefan Scholze; Sebastian Höppner; Paolo Del Giudice; René Schüffny (J. Signal Process. Syst., 2020)

Ultra-High Compression of Twiddle Factor ROMs in Multi-Core DSP for FMCW Radars. - Hector A. Gonzalez; Florian Kelber; Marco Stolba; Chen Liu 031; Bernhard Vogginger; Stefan Hänzsche; Stefan Scholze; Sebastian Höppner; Christian Mayr 001 (ISCAS, 2021)

A Single Battery Supply Power Concept for a Neuro Recording and Flexible Processing Chain in 22 nm. - Franz Marcus Schüffny; Stefan Hänzsche; Marc Berthel; Seyed Mohammad Ali Zeinolabedin; Stefan Scholze; Sebastian Höppner; Richard Miru George; Christian Mayr 001 (NorCAS, 2022)

A 16-Channel Fully Configurable Neural SoC With 1.52 $ mu$W/Ch Signal Acquisition, 2.79 $ mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI. - Seyed Mohammad Ali Zeinolabedin; Franz Marcus Schüffny; Richard George 001; Florian Kelber; Heiner Bauer; Stefan Scholze; Stefan Hänzsche; Marco Stolba; Andreas Dixius; Georg Ellguth; Dennis Walter; Sebastian Höppner; et al. (IEEE Trans. Biomed. Circuits Syst., 2022)

An Ultra-Low Area Digital-Assisted Neuro Recording System in 22nm FDSOI Technology. - Franz Marcus Schüffny; Sebastian Höppner; Stefan Hänzsche; Richard Miru George; Seyed Mohammad Ali Zeinolabedin; Christian Mayr 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 12-ADC 25-Core Smart MPSoC Using ABB in 22FDX for 77GHz MIMO Radars at 52.6mW Average Power. - Hector A. Gonzalez; Bernhard Vogginger; Chen Liu 031; Marco Stolba; Florian Kelber; Heiner Bauer; Stefan Hänzsche; Stefan Scholze; Marc Berthel; Tim Rosmeisl; Liyuan Guo; Dennis Walter; et al. (CICC, 2023)

A 3.3V Saturation-Aware Neurostimulator with Reset Functionality in 22 nm FDSOI. - Franz Marcus Schüffny; Stefan Hänzsche; Stephan Henker; Seyed Mohammad Ali Zeinolabedin; Stefan Scholze; Sebastian Höppner; Richard Miru George; Christian Mayr 001 (NEWCAS, 2023)