Realization of an Agent-Based Certificate Authority and Key Distribution. - Karsten Bsufka; Stefan Holst; Torge Schmidt (IATA, 1999)

A Mixed Finite-Element Discretization of the Energy-Transport Model for Semiconductors. - Stefan Holst; Ansgar Jüngel; Paola Pietra (SIAM J. Sci. Comput., 2003)

An Adaptive Mixed Scheme for Energy-Transport Simulations of Field-Effect Transistors. - Stefan Holst; Ansgar Jüngel; Paola Pietra (SIAM J. Sci. Comput., 2004)

An a priori error estimate for a monotone mixed finite-element discretization of a convection-diffusion problem. - Stefan Holst (Numerische Mathematik, 2008)

A diagnosis algorithm for extreme space compaction. - Stefan Holst; Hans-Joachim Wunderlich (DATE, 2009)

Test Encoding for Extreme Response Compaction. - Michael A. Kochte; Stefan Holst; Melanie Elm; Hans-Joachim Wunderlich (ETS, 2009)

Restrict Encoding for Mixed-Mode BIST. - Abdul Wahid Hakmi; Stefan Holst; Hans-Joachim Wunderlich; Jürgen Schlöffel; Friedrich Hapke; Andreas Glowatz (VTS, 2009)

Adaptive Debug and Diagnosis Without Fault Dictionaries. - Stefan Holst; Hans-Joachim Wunderlich (J. Electron. Test., 2009)

Embedded Test for Highly Accurate Defect Localization. - Abdullah Mumtaz; Michael E. Imhof; Stefan Holst; Hans-Joachim Wunderlich (Asian Test Symposium, 2011)

Structural Test for Graceful Degradation of NoC Switches. - Atefe Dalirsani; Stefan Holst; Melanie Elm; Hans-Joachim Wunderlich (ETS, 2011)

Scan Test Power Simulation on GPGPUs. - Stefan Holst; Eric Schneider; Hans-Joachim Wunderlich (Asian Test Symposium, 2012)

Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures. - Claus Braun; Stefan Holst; Hans-Joachim Wunderlich; Juan Manuel Castillo-Sanchez; Joachim Gross (ICCD, 2012)

Structural Test and Diagnosis for Graceful Degradation of NoC Switches. - Atefe Dalirsani; Stefan Holst; Melanie Elm; Hans-Joachim Wunderlich (J. Electron. Test., 2012)

Efficient location-based logic diagnosis of digital circuits. - Stefan Holst (2012)

Soft-error tolerant TCAMs for high-reliability packet classifications. - Infall Syafalni; Tsutomu Sasao; Xiaoqing Wen; Stefan Holst; Kohei Miyase (APCCAS, 2014)

Data-parallel simulation for fast and accurate timing validation of CMOS circuits. - Eric Schneider; Stefan Holst; Xiaoqing Wen; Hans-Joachim Wunderlich (ICCAD, 2014)

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. - Akihiro Tomita; Xiaoqing Wen; Yasuo Sato; Seiji Kajihara; Kohei Miyase; Stefan Holst; Patrick Girard 001; Mohammad Tehranipoor; Laung-Terng Wang (IEICE Trans. Inf. Syst., 2014)

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. - Koji Asada; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich; Jun Qian (ATS, 2015)

GPU-accelerated small delay fault simulation. - Eric Schneider; Stefan Holst; Michael A. Kochte; Xiaoqing Wen; Hans-Joachim Wunderlich (DATE, 2015)

A soft-error tolerant TCAM using partial don't-care keys. - Infall Syafalni; Tsutomu Sasao; Xiaoqing Wen; Stefan Holst; Kohei Miyase (ETS, 2015)

High-Throughput Logic Timing Simulation on GPGPUs. - Stefan Holst; Michael E. Imhof; Hans-Joachim Wunderlich (ACM Trans. Design Autom. Electr. Syst., 2015)

Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test. - Stephan Eggersglüß; Stefan Holst; Daniel Tille; Kohei Miyase; Xiaoqing Wen (ATS, 2016)

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test. - Stefan Holst; Eric Schneider; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Hans-Joachim Wunderlich; Michael A. Kochte (ATS, 2016)

Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation. - Fuqiang Li; Xiaoqing Wen; Kohei Miyase; Stefan Holst; Seiji Kajihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption. - Yucong Zhang; Stefan Holst; Xiaoqing Wen; Kohei Miyase; Seiji Kajihara; Jun Qian (ATS, 2017)

Analysis and mitigation or IR-Drop induced scan shift-errors. - Stefan Holst; Eric Schneider; Koshi Kawagoe; Michael A. Kochte; Kohei Miyase; Hans-Joachim Wunderlich; Seiji Kajihara; Xiaoqing Wen (ITC, 2017)

GPU-Accelerated Simulation of Small Delay Faults. - Eric Schneider; Michael A. Kochte; Stefan Holst; Xiaoqing Wen; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing. - Yucong Zhang; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Hans-Joachim Wunderlich; Jun Qian (ATS, 2018)

The impact of production defects on the soft-error tolerance of hardened latches. - Stefan Holst; Ruijun Ma; Xiaoqing Wen (ETS, 2018)

A Fault-Tolerant MPSoC For CubeSats. - Christian M. Fuchs; Pai H. Chou; Xiaoqing Wen; Nadia M. Murillo; Gianluca Furano; Stefan Holst; Antonis Tavoularis; Shyue-Kung Lu; Aske Plaat; Kostas Marinis (DFT, 2019)

STAHL: A Novel Scan-Test-Aware Hardened Latch Design. - Ruijun Ma; Stefan Holst; Xiaoqing Wen; Aibin Yan; Hui Xu (ETS, 2019)

Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses. - Stefan Holst; Eric Schneider; Michael A. Kochte; Xiaoqing Wen; Hans-Joachim Wunderlich (ITC, 2019)

Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test. - Stefan Holst; Shiling Shi; Xiaoqing Wen (PRDC, 2019)

Logic Fault Diagnosis of Hidden Delay Defects. - Stefan Holst; Matthias Kampmann; Alexander Sprenger; Jan Dennis Reimer; Sybille Hellebrand; Hans-Joachim Wunderlich; Xiaoqing Wen (ITC, 2020)

GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators. - Stefan Holst; Lim Bumun; Xiaoqing Wen (ATS, 2021)

On the Efficacy of Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption. - Yucong Zhang; Stefan Holst; Xiaoqing Wen; Kohei Miyase; Seiji Kajihara; Jun Qian (IEICE Trans. Inf. Syst., 2021)

On the Impact of Hardware Timing Errors on Stochastic Computing based Neural Networks. - Florian Neugebauer; Stefan Holst; Ilia Polian (ETS, 2022)

Power and Energy Safe Real-Time Multi-Core Task Scheduling. - Kalyan Baital; Amlan Chakrabarti; Biswadeep Chatterjee; Stefan Holst; Xiaoqing Wen (VLSID, 2022)

Evaluation and Test of Production Defects in Hardened Latches. - Ruijun Ma; Stefan Holst; Xiaoqing Wen; Aibin Yan; Hui Xu (IEICE Trans. Inf. Syst., 2022)

Guardband Optimization for the Preconditioned Conjugate Gradient Algorithm. - Natalia Lylina; Stefan Holst; Hanieh Jafarzadeh; Alexandra Kourfali; Hans-Joachim Wunderlich (DSN-W, 2023)

BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell. - Stefan Holst; Ruijun Ma; Xiaoqing Wen; Aibin Yan; Hui Xu (ETS, 2023)

Exploiting the Error Resilience of the Preconditioned Conjugate Gradient Method for Energy and Delay Optimization. - Natalia Lylina; Stefan Holst; Hanieh Jafarzadeh; Alexandra Kourfali; Hans-Joachim Wunderlich (IOLTS, 2023)

Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling. - Shiling Shi; Stefan Holst; Xiaoqing Wen (MCSoC, 2023)

Stock price movement prediction based on Stocktwits investor sentiment using FinBERT and ensemble SVM. - Jin-Xian Liu; Jenq-Shiou Leu; Stefan Holst (PeerJ Comput. Sci., 2023)

GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting. - Shiling Shi; Stefan Holst; Xiaoqing Wen (IEICE Trans. Inf. Syst., 2023)

Motion Classification by Utilizing Machine Learning for Acceleration Data. - Kenzaburo Ishizu; Toshimitsu Honda; Kohei Miyase; Stefan Holst; Shudai Ishikawa; Roshwin Sengupta; Ilia Polian (ICCE, 2025)

Highly Defect Detectable and SEU-Resilient Robust Scan-Test-Aware Latch Design. - Ruijun Ma; Stefan Holst; Hui Xu; Xiaoqing Wen; Senling Wang; Jiuqi Li; Aibin Yan (IEEE Trans. Very Large Scale Integr. Syst., 2025)