Predictable dynamic instruction scratchpad for simultaneous multithreaded processors. - Stefan Metzlaff; Sascha Uhrig; Jörg Mische; Theo Ungerer (MEDEA@PACT, 2008)

RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-core Processor. - Julian Wolf 002; Mike Gerdes 001; Florian Kluge; Sascha Uhrig; Jörg Mische; Stefan Metzlaff; Christine Rochange; Hugues Cassé; Pascal Sainrat; Theo Ungerer (ISORC, 2010)

Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability. - Theo Ungerer; Francisco J. Cazorla; Pascal Sainrat; Guillem Bernat; Zlatko Petrov; Christine Rochange; Eduardo Quiñones; Mike Gerdes 001; Marco Paolieri; Julian Wolf 002; Hugues Cassé; Sascha Uhrig; et al. (IEEE Micro, 2010)

A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardware. - Stefan Metzlaff; Irakli Guliashvili; Sascha Uhrig; Theo Ungerer (ARCS, 2011)

RTOS support for execution of parallelized hard real-time tasks on the MERASA multi-core processor. - Julian Wolf 002; Mike Gerdes 001; Florian Kluge; Sascha Uhrig; Jörg Mische; Stefan Metzlaff; Christine Rochange; Hugues Cassé; Pascal Sainrat; Theo Ungerer (Comput. Syst. Sci. Eng., 2011)

Replacement Policies for a Function-Based Instruction Memory: A Quantification of the Impact on Hardware Complexity and WCET Estimates. - Stefan Metzlaff; Theo Ungerer (ECRTS, 2012)

Impact of Instruction Cache and Different Instruction Scratchpads on the WCET Estimate. - Stefan Metzlaff; Theo Ungerer (HPCC-ICESS, 2012)

Analysable instruction memories for hard real-time systems. - Stefan Metzlaff (2012)

Leveraging transactional memory for a predictable execution of applications composed of hard real-time and best-effort tasks. - Stefan Metzlaff; Sebastian Weis; Theo Ungerer (RTNS, 2013)

A hard real-time capable multi-core SMT processor. - Marco Paolieri; Jörg Mische; Stefan Metzlaff; Mike Gerdes 001; Eduardo Quiñones; Sascha Uhrig; Theo Ungerer; Francisco J. Cazorla (ACM Trans. Embed. Comput. Syst., 2013)

Exploiting Intel TSX for fault-tolerant execution in safety-critical systems. - Florian Haas; Sebastian Weis; Stefan Metzlaff; Theo Ungerer (DFT, 2014)

A comparison of instruction memories from the WCET perspective. - Stefan Metzlaff; Theo Ungerer (J. Syst. Archit., 2014)

Accelerating Automated Driving and ADAS Using HW/SW Codesign. - Shubham Rai; Cecilia De la Parra; Martin Rapp; Jan Micha Borrmann; Nina Bretz; Stefan Metzlaff; Taha Soliman; Christoph Schorn (SOCC, 2024)