A Parallel-friendly Majority Gate to Accelerate In-memory Computation. - John Reuben; Stefan Pechmann (ASAP, 2020)

Simulating large neural networks embedding MLC RRAM as weight storage considering device variations. - Markus Fritscher; Johannes Knödtel; Daniel Reiser; Maen Mallah; Stefan Pechmann; Dietmar Fey; Marc Reichenbach (LASCAS, 2021)

Mitigating the Effects of RRAM Process Variation on the Accuracy of Artificial Neural Networks. - Markus Fritscher; Johannes Knödtel; Maen Mallah; Stefan Pechmann; Emilio Pérez-Bosch Quesada; Tommaso Rizzi; Christian Wenger; Marc Reichenbach (SAMOS, 2021)

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates. - John Reuben; Stefan Pechmann (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A Read Circuit Design for Multi-Level RRAM Cells Exhibiting Small Resistance Windows. - Stefan Pechmann; Amelie Hagelauer (MWSCAS, 2022)

A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays. - Stefan Pechmann; Amelie Hagelauer (SOCC, 2022)

A High-speed Low-power Sense Amplifier for the RRAM Array with Multi-level Reading Function using 130-nm Technology. - Running Guo; Ruolan Jia; Stefan Pechmann; Marc Reichenbach; Amelie Hagelauer (ICECS, 2023)

A RRAM Characterization System with Flexible Readout Operations using an Integrating ADC. - Ruolan Jia; Stefan Pechmann; Andrea Baroni; Christian Wenger; Amelie Hagelauer (PRIME, 2023)

Soft-Error Analysis of RRAM 1T1R Compute-In-Memory Core for Artificial Neural Networks. - Ruolan Jia; Stefan Pechmann; Markus Fritscher; Christian Wenger; Lei Zhang; Amelie Hagelauer (DCIS, 2024)

A Current Mirror Based Read Circuit Design with Multi-Level Capability for Resistive Switching Devices. - Stefan Pechmann; Eduardo Pérez; Christian Wenger; Amelie Hagelauer (ICEIC, 2024)

A Structured Approach for Embedded Memory Integration of Emerging Memory Technologies. - Stefan Pechmann; Thorsten Spätling; Peter Reichel; Roland Müller; Amelie Hagelauer (LASCAS, 2024)

A Reading Method for 2T2R RRAM Arrays Coding their Multiple States. - Running Guo; Stefan Pechmann; Amelie Hagelauer (MWSCAS, 2024)

Fully-Integrated Differential RRAM Cell Designs with Multi-Level Capability and Enhanced Read Margin. - Stefan Pechmann; Peter Reichel; Thorsten Spätling; Amelie Hagelauer (ISCAS, 2025)