TONIC: A timing database for VLSI design. - Gregory Schulte; Peter Tong; Stefan Rusu; Stuart Taylor (EURO-DAC, 1993)

Itanium processor clock design. - Utpal Desai; Simon M. Tam; Robert Kim; Ji Zhang; Stefan Rusu (ISPD, 2000)

The first IA-64 microprocessor. - Stefan Rusu; Gadi Singer (IEEE J. Solid State Circuits, 2000)

Clock generation and distribution for the first IA-64 microprocessor. - Simon Tam 001; Stefan Rusu; Utpal Nagarji Desai; Robert Kim; Ji Zhang; Ian Young 001 (IEEE J. Solid State Circuits, 2000)

Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract). - Stefan Rusu; Manoj Sachdev; Christer Svensson; Bram Nauta (ASP-DAC/VLSI Design, 2002)

Guest editorial. - Christian C. Enz; Stefan Rusu (IEEE J. Solid State Circuits, 2002)

A 1.5GHz third generation itanium® 2 processor. - Jason Stinson; Stefan Rusu (DAC, 2003)

A 400-MT/s 6.4-GB/s multiprocessor bus interface. - Harry Muljono; Beom-Taek Lee; Yanmei (Kathy) Tian; Yanbin (Eddie) Wang; Mubeen Atha; Tiffany Huang; Mitsuhiro Adachi; Stefan Rusu (IEEE J. Solid State Circuits, 2003)

A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache. - Stefan Rusu; Jason Stinson; Simon Tam 001; Justin Leung; Harry Muljono; Brian S. Cherkauer (IEEE J. Solid State Circuits, 2003)

Clock generation and distribution in high-performance processors. - Stefan Rusu (SoC, 2004)

Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache. - Stefan Rusu; Harry Muljono; Brian S. Cherkauer (IEEE Micro, 2004)

A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor. - Jonathan Chang; Stefan Rusu; Jonathan Shoemaker; Simon Tam 001; Ming Huang; Mizan Haque; Siufu Chiu; Kevin Truong; Mesbah Karim; Gloria Leong; Kiran Desai; Richard Goe; et al. (IEEE J. Solid State Circuits, 2005)

Introduction to the Special Issue on ESSCIRC'2004. - Rolf Koch; Stefan Rusu (IEEE J. Solid State Circuits, 2005)

A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache. - Stefan Rusu; Simon M. Tam; Harry Muljono; David Ayers; Jonathan Chang (ISSCC, 2006)

Microprocessors. - Stefan Rusu; Jim Warnock (ISSCC, 2007)

The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series. - Jonathan Chang; Ming Huang; Jonathan Shoemaker; John Benoit; Szu-Liang Chen; Wei Chen 129; Siufu Chiu; Raghuraman Ganesan; Gloria Leong; Venkata Lukka; Stefan Rusu; Durgesh Srivastava (IEEE J. Solid State Circuits, 2007)

Introduction to the Special Issue on ESSCIRC 2006. - Andreas Kaiser; Stefan Rusu (IEEE J. Solid State Circuits, 2007)

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. - Stefan Rusu; Simon M. Tam; Harry Muljono; David Ayers; Jonathan Chang; Brian S. Cherkauer; Jason Stinson; John Benoit; Raj Varada; Justin Leung; Rahul Dilip Limaye; Sujal Vora (IEEE J. Solid State Circuits, 2007)

Short Course. - Ian Galton; Jonathan Audy; Vadim Ivanov; Stefan Rusu; Seth R. Sanders (ISSCC, 2008)

Introduction to the Special Issue on the 33rd European Solid-State Circuits Conference (ESSCIRC 2007). - Andrea Baschirotto; Edoardo Charbon; Stefan Rusu (IEEE J. Solid State Circuits, 2008)

Power reduction techniques for an 8-core xeon® processor. - Stefan Rusu; Simon M. Tam; Harry Muljono; Jason Stinson; David Ayers; Jonathan Chang; Raj Varada; Matt Ratta; Sailesh Kottapalli; Sujal Vora (ESSCIRC, 2009)

Multi-domain processors. - Stefan Rusu (ISSCC, 2009)

A 45nm 8-core enterprise Xeon® processor. - Stefan Rusu; Simon M. Tam; Harry Muljono; Jason Stinson; David Ayers; Jonathan Chang; Raj Varada; Matt Ratta; Sailesh Kottapalli (ISSCC, 2009)

Introduction to the Special Issue on the 34th ESSCIRC. - Kari A. I. Halonen; Kofi A. A. Makinwa; Stefan Rusu (IEEE J. Solid State Circuits, 2009)

A 45 nm 8-Core Enterprise Xeon¯ Processor. - Stefan Rusu; Simon M. Tam; Harry Muljono; Jason Stinson; David Ayers; Jonathan Chang; Raj Varada; Matt Ratta; Sailesh Kottapalli; Sujal Vora (IEEE J. Solid State Circuits, 2010)

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family. - Stefan Rusu; Harry Muljono; David Ayers; Simon M. Tam; Wei Chen 129; Aaron Martin; Shenggao Li; Sujal Vora; Raj Varada; Eddie Wang (ISSCC, 2014)

Introduction to the Special Issue on the 39th European Solid-State Circuits Conference (ESSCIRC). - Yann Deval; Stefan Rusu (IEEE J. Solid State Circuits, 2014)

Introduction to the Special Section on the 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC). - Stefan Rusu; Gregory Chen (IEEE J. Solid State Circuits, 2015)

A 22 nm 15-Core Enterprise Xeon® Processor Family. - Stefan Rusu; Harry Muljono; David Ayers; Simon M. Tam; Wei Chen 129; Aaron Martin; Shenggao Li; Sujal Vora; Raj Varada; Eddie Wang (IEEE J. Solid State Circuits, 2015)

Welcome to 2016 Hot Chips. - Stefan Rusu (Hot Chips Symposium, 2016)

Introduction to the Special Issue on the 41st European Solid-State Circuits Conference (ESSCIRC). - Andrea Mazzanti; Bram Nauta; Stefan Rusu (IEEE J. Solid State Circuits, 2016)

A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing. - Mu-Shan Lin; Tze-Chiang Huang; Chien-Chun Tsai; King-Ho Tam; Kenny Cheng-Hsiang Hsieh; Tom Chen 002; Wen-Hung Huang; Jack Hu; Yu-Chi Chen; Sandeep Kumar Goel; Chin-Ming Fu; Stefan Rusu; et al. (VLSI Circuits, 2019)

Guest Editorial: Special Section on the 48th European Solid-State Circuits Conference (ESSCIRC). - Ángel Rodríguez-Vázquez; Kaushik Sengupta; Stefan Rusu (IEEE J. Solid State Circuits, 2019)

Hot Chips 30. - John Kubiatowicz; Stefan Rusu (IEEE Micro, 2019)

A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. - Mu-Shan Lin; Tze-Chiang Huang; Chien-Chun Tsai; King-Ho Tam; Kenny Cheng-Hsiang Hsieh; Ching-Fang Chen; Wen-Hung Huang; Chi-Wei Hu; Yu-Chi Chen; Sandeep Kumar Goel; Chin-Ming Fu; Stefan Rusu; et al. (IEEE J. Solid State Circuits, 2020)

TSMC in the Silicon Photonics Era - an Electrical Perspective. - Mikael Sahrling; Shenggao Li; Frank Lee 004; Stefan Rusu (OFC, 2025)