Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. - Cecilia Metra; Stefano Di Francescantonio; Bruno Riccò; T. M. Mak (DFT, 2001)

On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits. - Cecilia Metra; Stefano Di Francescantonio; Giuseppe Marrale (DFT, 2002)

Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. - Cecilia Metra; Stefano Di Francescantonio; T. M. Mak (ITC, 2002)

On-Chip Clock Faults' Detector. - Cecilia Metra; Michele Favalli; Stefano Di Francescantonio; Bruno Riccò (J. Electron. Test., 2002)

Automatic Modification of Sequential Circuits for Self-Checking Implementation. - Cecilia Metra; Stefano Di Francescantonio; Martin Omaña 001 (DFT, 2003)

Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults. - Cecilia Metra; Stefano Di Francescantonio; Michele Favalli; Bruno Riccò (Microelectron. J., 2003)

Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing. - Cecilia Metra; Stefano Di Francescantonio; T. M. Mak (IEEE Trans. Computers, 2004)