Crypto Accelerators for Power-Efficient and Real-Time on-Chip Implementation of Secure Algorithms. - Luca Baldanzi; Luca Crocetti; Stefano Di Matteo; Luca Fanucci; Sergio Saponara; Patrice Hameau (ICECS, 2019)

CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes. - Pietro Nannipieri; Luca Baldanzi; Luca Crocetti; Stefano Di Matteo; Francesco Falaschi; Luca Fanucci; Sergio Saponara (ApplePies, 2021)

A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms. - Pietro Nannipieri; Stefano Di Matteo; Luca Zulberti; Francesco Albicocchi; Sergio Saponara; Luca Fanucci (IEEE Access, 2021)

SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative. - Pietro Nannipieri; Matteo Bertolucci; Luca Baldanzi; Luca Crocetti; Stefano Di Matteo; Francesco Falaschi; Luca Fanucci; Sergio Saponara (Microprocess. Microsystems, 2021)

Design and Implementation on FPGA of a HW Accelerator for Post-Quantum RLWE Polynomial Operations. - Stefano Di Matteo; Sergio Saponara; Riccardo Locatelli (ApplePies, 2022)

Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source. - Luca Crocetti; Stefano Di Matteo; Pietro Nannipieri; Luca Fanucci; Sergio Saponara (Entropy, 2022)

VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative. - Pietro Nannipieri; Stefano Di Matteo; Luca Baldanzi; Luca Crocetti; Luca Zulberti; Sergio Saponara; Luca Fanucci (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A PUF-Based Secure Boot for RISC-V Architectures. - Stefano Di Matteo; Luca Zulberti; Federico Cosimo Lapenna; Pietro Nannipieri; Luca Crocetti; Luca Fanucci; Sergio Saponara (ApplePies, 2023)

Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative. - Pietro Nannipieri; Stefano Di Matteo; Luca Crocetti; Luca Zulberti; Luca Fanucci; Sergio Saponara (ApplePies, 2023)

Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures. - Daniele Rossi 001; Nicasio Canino; Stefano Di Matteo; Sergio Saponara; Vasileios Tenentes (SEEDA-CECNSM, 2023)

VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library. - Stefano Di Matteo; Matteo Lo Gerfo; Sergio Saponara (IEEE Access, 2023)

Innovative Plug-and-Play System for Electrification of Wheel-Chairs. - Federico Pacini; Stefano Di Matteo; Pierpaolo Dini; Luca Fanucci; Francesco Bucchi (IEEE Access, 2023)

RTL Flow for the Power Side-Channel Resilience Assessment of a Post-Quantum SHA-3 Accelerator. - Vasileios Tenentes; Stefano Di Matteo; Christos Zonios; Daniele Rossi 001; Sergio Saponara (MOCAST, 2024)

HW-SW Interface Design and Implementation for Error Logging and Reporting for RAS Improvement. - Nicasio Canino; Stefano Di Matteo; Daniele Rossi 001; Sergio Saponara (IEEE Access, 2024)

CRYPHTOR: A Memory-Unified NTT-Based Hardware Accelerator for Post-Quantum CRYSTALS Algorithms. - Stefano Di Matteo; Ivan Sarno; Sergio Saponara (IEEE Access, 2024)

On hardware acceleration of quantum-resistant FOTA systems in automotive. - Pericle Perazzo; Stefano Di Matteo; Gianluca Dini; Sergio Saponara (Comput. Electr. Eng., 2024)

TYRCA: A RISC-V Tightly-Coupled Accelerator for Code-Based Cryptography. - Alessandra Dolmeta; Stefano Di Matteo; Emanuele Valea; Mikael Carmona; Antoine Loiseau; Maurizio Martina; Guido Masera (DATE, 2025)

Hardware Design of an Advanced-Feature Cryptographic Tile Within the European Processor Initiative. - Pietro Nannipieri; Luca Crocetti; Stefano Di Matteo; Luca Fanucci; Sergio Saponara (IEEE Trans. Computers, 2025)