A voltage-controlled oscillator for IEEE 802.11a and HiperLAN2 application. - Andrea Giovanni Bonfanti; Salvatore Levantino; Stefano Pellerano; Carlo Samori; Andrea L. Lacaita; Felice Torrisi (ESSCIRC, 2003)

Phase noise in digital frequency dividers. - Salvatore Levantino; Luca Romanò; Stefano Pellerano; Carlo Samori; Andrea L. Lacaita (IEEE J. Solid State Circuits, 2004)

A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider. - Stefano Pellerano; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (IEEE J. Solid State Circuits, 2004)

Fully-integrated frequency synthesizers for multi-standard WLAN applications. - Stefano Pellerano (2004)

A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction. - Yorgos Palaskas; Stewart S. Taylor; Stefano Pellerano; Ian A. Rippke; Ralph E. Bishop; Ashoke Ravi; Hasnain Lakdawala; Krishnamurthy Soumyanath (CICC, 2005)

A 5GHz 108Mb/s 2x2 MIMO Transceiver with Fully Integrated +16dBm PAs in 90nm CMOS. - Yorgos Palaskas; Ashoke Ravi; Stefano Pellerano; Brent R. Carlton; Mostafa A. Elmala; Ralph E. Bishop; Gaurab Banerjee; Rich B. Nicholls; Stanley K. Ling; Stewart S. Taylor; Krishnamurthy Soumyanath (ISSCC, 2006)

A 5-GHz 108-Mb/s 2 $ times$2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm ${ rm P}_{ rm 1dB}$ Power Amplifiers in 90-nm CMOS. - Yorgos Palaskas; Ashoke Ravi; Stefano Pellerano; Brent R. Carlton; Mostafa A. Elmala; Ralph E. Bishop; Gaurab Banerjee; Rich B. Nicholls; Stanley K. Ling; Nati Dinur; Stewart S. Taylor; Krishnamurthy Soumyanath (IEEE J. Solid State Circuits, 2006)

A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process. - Yorgos Palaskas; Stewart S. Taylor; Stefano Pellerano; Ian A. Rippke; Ralph E. Bishop; Ashoke Ravi; Hasnain Lakdawala; Krishnamurthy Soumyanath (IEEE J. Solid State Circuits, 2006)

A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS. - Stefano Pellerano; Yorgos Palaskas; Krishnamurthy Soumyanath (ESSCIRC, 2007)

MIMO techniques for high data rate radio communications. - Yorgos Palaskas; Ashoke Ravi; Stefano Pellerano (CICC, 2008)

A 1.7-GHz 1.5-mW digitally-controlled FBAR oscillator with 0.03-ppb resolution. - Hiroyuki Ito; Hasnain Lakdawala; Ashoke Ravi; Stefano Pellerano; Rick Ruby; Krishnamurthy Soumyanath; Kazuya Masu (ESSCIRC, 2008)

A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS. - Stefano Pellerano; Rajarshi Mukhopadhyay; Ashoke Ravi; Joy Laskar; Yorgos Palaskas (ISSCC, 2008)

A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS. - Stefano Pellerano; Yorgos Palaskas; Krishnamurthy Soumyanath (IEEE J. Solid State Circuits, 2008)

A mm-wave power harvesting RFID tag in 90nm CMOS. - Stefano Pellerano; Javier Alvarado Jr.; Yorgos Palaskas (CICC, 2009)

A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving. - Paolo Madoglio; Ashoke Ravi; Luis Cuellar 001; Stefano Pellerano; Parmoon Seddighrad; Ismael Lomeli; Yorgos Palaskas (ESSCIRC, 2009)

A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS. - Stefano Pellerano; Paolo Madoglio; Yorgos Palaskas (ISSCC, 2009)

A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS. - Stefano Pellerano; Paolo Madoglio; Yorgos Palaskas (IEEE J. Solid State Circuits, 2009)

A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving. - Paolo Madoglio; Ashoke Ravi; Luis Cuellar 001; Stefano Pellerano; Parmoon Seddighrad; Ismael Lomeli; Yorgos Palaskas (IEEE J. Solid State Circuits, 2010)

A mm-Wave Power-Harvesting RFID Tag in 90 nm CMOS. - Stefano Pellerano; Javier Alvarado Jr.; Yorgos Palaskas (IEEE J. Solid State Circuits, 2010)

A 12-element 60GHz CMOS phased array transmitter on LTCC package with integrated antennas. - Ajay Balankutty; Stefano Pellerano; Telesphor Kamgaing; Kranti Tantwai; Yorgos Palaskas (A-SSCC, 2011)

A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management. - Kailash Chandrashekar; Stefano Pellerano; Paolo Madoglio; Ashoke Ravi; Yorgos Palaskas (ISSCC, 2012)

32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver. - Hasnain Lakdawala; Mark Schaecher; Chang-Tsung Fu; Rahul Dilip Limaye; Jon Duster; Yulin Tan; Ajay Balankutty; Erkan Alpman; Chun C. Lee; Satoshi Suzuki; Brent R. Carlton; Hyung Seok Kim; et al. (ISSCC, 2012)

A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS. - Paolo Madoglio; Ashoke Ravi; Hongtao Xu; Kailash Chandrashekar; Marian Verhelst; Stefano Pellerano; Luis Cuellar 001; Mariano Aguirre; Masoud Sajadieh; Ofir B. Degani; Hasnain Lakdawala; Yorgos Palaskas (ISSCC, 2012)

A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS. - Yulin Tan; Jon Duster; Chang-Tsung Fu; Erkan Alpman; Ajay Balankutty; Chun C. Lee; Ashoke Ravi; Stefano Pellerano; Kailash Chandrashekar; Hyung Seok Kim; Brent R. Carlton; Satoshi Suzuki; et al. (VLSIC, 2012)

A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS. - Ashoke Ravi; Paolo Madoglio; Hongtao Xu; Kailash Chandrashekar; Marian Verhelst; Stefano Pellerano; Luis Cuellar 001; Mariano Aguirre-Hernandez; Masoud Sajadieh; J. E. Zarate-Roldan; Ofir Bochobza-Degani; Hasnain Lakdawala; et al. (IEEE J. Solid State Circuits, 2012)

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver. - Hasnain Lakdawala; Mark Schaecher; Chang-Tsung Fu; Rahul Dilip Limaye; Jon Duster; Yulin Tan; Ajay Balankutty; Erkan Alpman; Chun C. Lee; Khoa Minh Nguyen; Hyung-Jin Lee; Ashoke Ravi; et al. (IEEE J. Solid State Circuits, 2013)

Session 19 overview: Advanced wireless techniques: Wireless subcommittee. - Stefano Pellerano; Koji Takinami (ISSCC, 2015)

F5: Advanced RF CMOS transmitter techniques. - Piet Wambacq; Stefano Pellerano; Sven Mattisson; Shouhei Kousai; Ali Afsahi; Taizo Yamawaki (ISSCC, 2015)

Wi-Fi RF energy harvesting for battery-free wearable radio platforms. - Vamsi Talla; Stefano Pellerano; Hongtao Xu; Ashoke Ravi; Yorgos Palaskas (IEEE RFID, 2015)

F3: Radio architectures and circuits towards 5G. - Stefano Pellerano; Ahmad Mirzaei; Chih-Ming Hung; Jan Craninckx; Kenichi Okada 001; Vojkan Vidojkovic (ISSCC, 2016)

13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications. - Paolo Madoglio; Hongtao Xu; Kailash Chandrashekar; Luis Cuellar 001; Muhammad Faisal; Yee William Li; Hyung Seok Kim; Khoa Minh Nguyen; Yulin Tan; Brent R. Carlton; Vaibhav A. Vaidya; Yanjie Wang; et al. (ISSCC, 2017)

13.8 A 24dBm 2-to-4.3GHz wideband digital Power Amplifier with built-in AM-PM distortion self-compensation. - Jong Seok Park 001; Yanjie Wang; Stefano Pellerano; Christopher D. Hull; Hua Wang 006 (ISSCC, 2017)

EE2: Intelligent machines: Will the technological singularity happen? - Stefano Pellerano; Sungdae Choi; Jan M. Rabaey (ISSCC, 2017)

FinFET for mm Wave - Technology and Circuit Design Challenges. - Steven Callender; Woorim Shin; Hyung-Jin Lee; Stefano Pellerano; Christopher D. Hull (BCICTS, 2018)

Session 4 overview: mm-Wave radios for 5G and beyond: Wireless subcommittee. - Chun-Huat Heng; David McLaurin; Stefano Pellerano (ISSCC, 2018)

Session 28 overview: Wireless connectivity: Wireless subcommittee. - Howard C. Luong; Kyoo Hyun Lim; Stefano Pellerano (ISSCC, 2018)

Session 9 overview: Wireless transceivers and techniques: Wireless subcommittee. - Alan Wong; Xin He; Stefano Pellerano (ISSCC, 2018)

Architecture and Circuit Choices for 5G Millimeter-Wave Beamforming Transceivers. - Peter Sagazio; Steven Callender; Woorim Shin; Oner Orhan; Stefano Pellerano; Christopher D. Hull (IEEE Commun. Mag., 2018)

802.11g/n Compliant Fully Integrated Wake-Up Receiver With -72-dBm Sensitivity in 14-nm FinFET CMOS. - Erkan Alpman; Ahmad Khairi; Richard Dorrance; Minyoung Park; V. Srinivasa Somayazulu; Jeffrey R. Foerster; Ashoke Ravi; Jeyanandh Paramesh; Stefano Pellerano (IEEE J. Solid State Circuits, 2018)

A CMOS Wideband Current-Mode Digital Polar Power Amplifier With Built-In AM-PM Distortion Self-Compensation. - Jong Seok Park 001; Yanjie Wang; Stefano Pellerano; Christopher D. Hull; Hua Wang 006 (IEEE J. Solid State Circuits, 2018)

A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology. - Stefano Pellerano; Steven Callender; Woorim Shin; Yanjie Wang; Somnath Kundu; Abhishek Agrawal; Peter Sagazio; Brent R. Carlton; Farhana Sheikh; Arnaud Amadjikpe; William J. Lambert; Divya Shree Vemparala; et al. (ISSCC, 2019)

An $E$ -Band Power Amplifier With 26.3% PAE and 24-GHz Bandwidth in 22-nm FinFET CMOS. - Steven Callender; Stefano Pellerano; Christopher D. Hull (IEEE J. Solid State Circuits, 2019)

25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS. - Somnath Kundu; Likai Chai; Kailash Chandrashekar; Stefano Pellerano; Brent R. Carlton (ISSCC, 2020)

19.1 A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers. - Bishnu Patra; Jeroen P. G. van Dijk; Sushil Subramanian; Andrea Corna; Xiao Xue 004; Charles Jeon; Farhana Sheikh; Esdras Juarez Hernandez; Brando Perez Esparza; Huzaifa Rampurawala; Brent R. Carlton; Nodar Samkharadze; et al. (ISSCC, 2020)

A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons. - Jeroen Petrus Gerardus van Dijk; Bishnu Patra; Sushil Subramanian; Xiao Xue 004; Nodar Samkharadze; Andrea Corna; Charles Jeon; Farhana Sheikh; Esdras Juarez Hernandez; Brando Perez Esparza; Huzaifa Rampurawala; Brent R. Carlton; et al. (IEEE J. Solid State Circuits, 2020)

Designing a DDS-Based SoC for High-Fidelity Multi-Qubit Control. - Jeroen P. G. van Dijk; Bishnu Patra; Stefano Pellerano; Edoardo Charbon; Fabio Sebastiano; Masoud Babaie (IEEE Trans. Circuits Syst., 2020)

A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology. - Jong Seok Park 001; Sushil Subramanian; Lester Lampert; Todor Mladenov; Ilya Klotchkov; Dileep Kurian; Esdras Juárez-Hernández; Brando Perez Esparza; Sirisha Rani Kale; K. T. Asma Beevi; Shavindra P. Premaratne; Thomas Watson 006; et al. (ISSCC, 2021)

A Reconfigurable Non-Uniform Power-Combining V-Band PA With +17.9 dBm Psat and 26.5% PAE in 16-nm FinFET CMOS. - Kun-Da Chu; Steven Callender; Yanjie Wang; Jacques Christophe Rudell; Stefano Pellerano; Christopher D. Hull (IEEE J. Solid State Circuits, 2021)

A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS. - Somnath Kundu; Likai Chai; Kailash Chandrashekar; Stefano Pellerano; Brent R. Carlton (IEEE J. Solid State Circuits, 2021)

A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits. - Jongseok Park 001; Sushil Subramanian; Lester Lampert; Todor Mladenov; Ilya Klotchkov; Dileep Kurian; Esdras Juarez Hernandez; Brando Perez Esparza; Sirisha Rani Kale; K. T. Asma Beevi; Shavindra P. Premaratne; Thomas Watson 006; et al. (IEEE J. Solid State Circuits, 2021)

Cryogenic CMOS for Qubit Control and Readout. - Stefano Pellerano; Sushil Subramanian; Jong Seok Park 001; Bishnu Patra; Todor Mladenov; Xiao Xue 004; Lieven M. K. Vandersypen; Masoud Babaie; Edoardo Charbon; Fabio Sebastiano (CICC, 2022)

Innovations for Intelligent Edge. - Vida Ilderem; Stefano Pellerano; Jim Tschanz; Tanay Karnik; Vivek De (ESSCIRC, 2022)

A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology. - Steven Callender; Amy Whitcombe; Abhishek Agrawal; Ritesh Bhat; Mustafijur Rahman; Chun C. Lee; Peter Sagazio; Georgios C. Dogiamis; Brent R. Carlton; Mark Chakravorti; Stefano Pellerano; Christopher D. Hull (ISSCC, 2022)

A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup. - Somnath Kundu; Timo Huusari; Hao Luo; Abhishek Agrawal; Eduardo Alban; Sarah Shahraini; Thao Xiong; Dan Lake; Stefano Pellerano; Jason Mix; Nasser A. Kurd; Mohamed Abdel-moneum; et al. (ISSCC, 2022)

A 6.0mW 3.8GS/s 7b VTC/TDC-Assisted Interleaved SAR ADC with 13GHz ERBW. - Amy Whitcombe; Chun C. Lee; Asma Kuriparambil Thekkumpate; Somnath Kundu; Jaykant Timbadiya; Abhishek Agrawal; Brent R. Carlton; Peter Sagazio; Stefano Pellerano; Christopher D. Hull (VLSI Technology and Circuits, 2022)

A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET. - Steven Callender; Abhishek Agrawal; Amy Whitcombe; Ritesh Bhat; Mustafijur Rahman; Chun C. Lee; Peter Sagazio; Georgios C. Dogiamis; Brent R. Carlton; Christopher D. Hull; Stefano Pellerano (IEEE J. Solid State Circuits, 2022)

A 128Gb/s 1.95pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET. - Abhishek Agrawal; Amy Whitcombe; Woorim Shin; Ritesh Bhat; Somnath Kundu; Peter Sagazio; Hariprasad Chandrakumar; Thomas William Brown; Brent R. Carlton; Christopher D. Hull; Steven Callender; Stefano Pellerano (ISSCC, 2023)

A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW. - Amy Whitcombe; Chun C. Lee; Asma Kuriparambil Thekkumpate; Somnath Kundu; Jaykant Timbadiya; Abhishek Agrawal; Brent R. Carlton; Peter Sagazio; Stefano Pellerano; Christopher D. Hull (IEEE J. Solid State Circuits, 2023)

A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET. - Abhishek Agrawal; Amy Whitcombe; Woorim Shin; Ritesh Bhat; Somnath Kundu; Peter Sagazio; Hariprasad Chandrakumar; Thomas William Brown; Brent R. Carlton; Christopher Dennis Hull; Steven Callender; Stefano Pellerano (IEEE J. Solid State Circuits, 2023)

D-Band meets FinFET: Fully-Integrated Transmitter and Receiver Architectures for 100+Gb/s Links. - Steven Callender; Abhishek Agrawal; Amy Whitcombe; Stefano Pellerano (BCICTS, 2024)

22.3 A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking. - Amy Whitcombe; Somnath Kundu; Hariprasad Chandrakumar; Abhishek Agrawal; Thomas William Brown; Steven Callender; Brent R. Carlton; Stefano Pellerano (ISSCC, 2024)

A Scalable mK Cryo-CMOS Demultiplexer Chip for Voltage Biasing and High-Speed Control of Silicon Qubit Gates. - Sushil Subramanian; Todor Mladenov; Simon Schaal; Bishnu Patra; Lester Lampert; Nancy K. Robinson; Jeanette Roberts; Stefano Pellerano (VLSI Technology and Circuits, 2024)