A Prolog-based design environment for the high-level synthesis of application-specific architectures. - Panagiotis Tsanakas; George K. Papakonstantinou; Stefanos Kaxiras (Microprocessing and Microprogramming, 1991)

PSM: software tool for simulating, prototyping, and monitoring of multiprocessor systems. - Andreas Stafylopatis; I. Papakonstantinou; Stefanos Kaxiras (Inf. Softw. Technol., 1992)

The GLOW Cache Coherence Protocol Extensions for Widely Shared Data. - Stefanos Kaxiras; James R. Goodman (International Conference on Supercomputing, 1996)

Kiloprocessor Extensions to SCI. - Stefanos Kaxiras (IPPS, 1996)

DataScalar Architectures. - Doug Burger; Stefanos Kaxiras; James R. Goodman (ISCA, 1997)

A Study of Three Dynamic Approaches to Handle Widely Shared Data in Shared-memory Multiprocessors. - Stefanos Kaxiras; Stein Gjessing; James R. Goodman (International Conference on Supercomputing, 1998)

Improving CC-NUMA Performance Using Instruction-Based Prediction. - Stefanos Kaxiras; James R. Goodman (HPCA, 1999)

DataScalar: A memory-centric approach to computing. - Stefanos Kaxiras; Doug Burger; James R. Goodman (J. Syst. Archit., 1999)

Coherence Communication Prediction in Shared-Memory Multiprocessors. - Stefanos Kaxiras; Cliff Young (HPCA, 2000)

Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power. - Stefanos Kaxiras; Zhigang Hu; Girija J. Narlikar; Rae McLellan (PACS, 2000)

Distributed vector architectures. - Stefanos Kaxiras (J. Syst. Archit., 2000)

Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads. - Stefanos Kaxiras; Girija J. Narlikar; Alan D. Berenbaum; Zhigang Hu (CASES, 2001)

Cache decay: exploiting generational behavior to reduce cache leakage power. - Stefanos Kaxiras; Zhigang Hu; Margaret Martonosi (ISCA, 2001)

Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior. - Zhigang Hu; Margaret Martonosi; Stefanos Kaxiras (ISCA, 2002)

Managing leakage for transient data: decay and quasi-static 4T memory cells. - Zhigang Hu; Philo Juang; Phil Diodato; Stefanos Kaxiras; Kevin Skadron; Margaret Martonosi; Douglas W. Clark (ISLPED, 2002)

Implementing Decay Techniques using 4T Quasi-Static Memory Cells. - Philo Juang; Phil Diodato; Stefanos Kaxiras; Kevin Skadron; Zhigang Hu; Margaret Martonosi; Douglas W. Clark (IEEE Comput. Archit. Lett., 2002)

Let caches decay: reducing leakage energy via exploitation of cache generational behavior. - Zhigang Hu; Stefanos Kaxiras; Margaret Martonosi (ACM Trans. Comput. Syst., 2002)

TCP: Tag Correlating Prefetchers. - Zhigang Hu; Margaret Martonosi; Stefanos Kaxiras (HPCA, 2003)

IPStash: a Power-Efficient Memory Architecture for IP-lookup. - Stefanos Kaxiras; Georgios Keramidas (MICRO, 2003)

4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors. - Stefanos Kaxiras; Polychronis Xekalakis (ISLPED, 2004)

Implementing branch-predictor decay using quasi-static memory cells. - Philo Juang; Kevin Skadron; Margaret Martonosi; Zhigang Hu; Douglas W. Clark; Phil Diodato; Stefanos Kaxiras (ACM Trans. Archit. Code Optim., 2004)

IPStash: a set-associative memory approach for efficient IP-lookup. - Stefanos Kaxiras; Georgios Keramidas (INFOCOM, 2005)

A simple mechanism to adapt leakage-control policies to temperature. - Stefanos Kaxiras; Polychronis Xekalakis; Georgios Keramidas (ISLPED, 2005)

Dynamic Dictionary-Based Data Compression for Level-1 Caches. - Georgios Keramidas; Konstantinos Aisopos; Stefanos Kaxiras (ARCS, 2006)

Topic 18: Embedded Parallel Systems. - Jürgen Teich; Stefanos Kaxiras; Toomas P. Plaks; Krisztián Flautner (Euro-Par, 2006)

Modeling Cache Sharing on Chip Multiprocessor Architectures. - Pavlos Petoumenos; Georgios Keramidas; Håkan Zeffer; Stefanos Kaxiras; Erik Hagersten (IISWC, 2006)

Preventing Denial-of-Service Attacks in Shared CMP Caches. - Georgios Keramidas; Pavlos Petoumenos; Stefanos Kaxiras; Alexandros Antonopoulos; Dimitrios N. Serpanos (SAMOS, 2006)

Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors. - Juan M. Cebrian; Juan L. Aragón; José M. García 001; Stefanos Kaxiras (Conf. Computing Frontiers, 2007)

Using value locality to reduce memory encryption overhead in embedded processors. - Georgios Keramidas; Pavlos Petoumenos; Alexandros Antonopoulos; Stefanos Kaxiras; Dimitrios N. Serpanos (ETFA, 2007)

Applying Decay to Reduce Dynamic Power in Set-Associative Caches. - Georgios Keramidas; Polychronis Xekalakis; Stefanos Kaxiras (HiPEAC, 2007)

Cache replacement based on reuse-distance prediction. - Georgios Keramidas; Pavlos Petoumenos; Stefanos Kaxiras (ICCD, 2007)

Low power microarchitecture with instruction reuse. - Frederico Pratas; Georgi Gaydadjiev; Mladen Berekovic; Leonel Sousa; Stefanos Kaxiras (Conf. Computing Frontiers, 2008)

Non deterministic caches: a simple and effective defense against side channel attacks. - Georgios Keramidas; Alexandros Antonopoulos; Dimitrios N. Serpanos; Stefanos Kaxiras (Des. Autom. Embed. Syst., 2008)

Computer Architecture Techniques for Power-Efficiency - Stefanos Kaxiras; Margaret Martonosi (Morgan & Claypool Publishers, 2008)

Instruction Precomputation for Fault Detection. - Demid Borodin; Ben H. H. Juurlink; Stefanos Kaxiras (DSD, 2009)

Efficient microarchitecture policies for accurately adapting to power constraints. - Juan M. Cebrian; Juan L. Aragón; José M. García 001; Pavlos Petoumenos; Stefanos Kaxiras (IPDPS, 2009)

Instruction-based reuse-distance prediction for effective cache management. - Pavlos Petoumenos; Georgios Keramidas; Stefanos Kaxiras (ICSAMOS, 2009)

Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches. - Georgios Keramidas; Polychronis Xekalakis; Stefanos Kaxiras (Trans. High Perform. Embed. Archit. Compil., 2009)

MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance. - Pavlos Petoumenos; Georgia Psychou; Stefanos Kaxiras; Juan Manuel Cebrian Gonzalez; Juan L. Aragón (ARCS, 2010)

Where replacement algorithms fail: a thorough analysis. - Georgios Keramidas; Pavlos Petoumenos; Stefanos Kaxiras (Conf. Computing Frontiers, 2010)

Interval-based models for run-time DVFS orchestration in superscalar processors. - Georgios Keramidas; Vasileios Spiliopoulos 001; Stefanos Kaxiras (Conf. Computing Frontiers, 2010)

Teaching Introduction to Computing Through a Project-Based Collaborative Learning Approach. - Nikolaos M. Avouris; Stefanos Kaxiras; Odysseas G. Koufopavlou; Kyriakos N. Sgarbas; Polyxeni Stathopoulou (Panhellenic Conference on Informatics, 2010)

SARC Coherence: Scaling Directory Cache Coherence in Performance and Power. - Stefanos Kaxiras; Georgios Keramidas (IEEE Micro, 2010)

Multicore Cache Simulations Using Heterogeneous Computing on General Purpose and Graphics Processors. - Georgios Keramidas; Nikolaos Strikos; Stefanos Kaxiras (DSD, 2011)

Token3D: Reducing Temperature in 3D Die-Stacked CMPs through Cycle-Level Power Control Mechanisms. - Juan M. Cebrian; Juan L. Aragón; Stefanos Kaxiras (Euro-Par (1), 2011)

Green governors: A framework for Continuously Adaptive DVFS. - Vasileios Spiliopoulos 001; Stefanos Kaxiras; Georgios Keramidas (IGCC, 2011)

Poster: DVFS management in real-processors. - Vasileios Spiliopoulos 001; Georgios Keramidas; Stefanos Kaxiras; Konstantinos Efstathiou 002 (ICS, 2011)

Power Token Balancing: Adapting CMPs to Power Constraints for Parallel Multithreaded Workloads. - Juan M. Cebrian; Juan L. Aragón; Stefanos Kaxiras (IPDPS, 2011)

Leakage-efficient design of value predictors through state and non-state preserving techniques. - Juan M. Cebrian; Juan L. Aragón; José M. García 001; Stefanos Kaxiras (J. Supercomput., 2011)

Complexity-effective multicore coherence. - Alberto Ros 001; Stefanos Kaxiras (PACT, 2012)

Embedded reconfigurable architectures. - Stephan Wong; Luigi Carro; Stamatios Kavvadias; Georgios Keramidas; Francesco Papariello; Claudio Scordino; Roberto Giorgi; Stefanos Kaxiras (CASES, 2012)

Power-Sleuth: A Tool for Investigating Your Program's Power Behavior. - Vasileios Spiliopoulos 001; Andreas Sembrant; Stefanos Kaxiras (MASCOTS, 2012)

A framework for efficient cache resizing. - Georgios Keramidas; Chrysovalantis Datsios; Stefanos Kaxiras (ICSAMOS, 2012)

Efficient, snoopless, System-on-Chip coherence. - Stefanos Kaxiras; Alberto Ros 001 (SoCC, 2012)

Towards more efficient execution: a decoupled access-execute approach. - Konstantinos Koukos; David Black-Schaffer; Vasileios Spiliopoulos 001; Stefanos Kaxiras (ICS, 2013)

A new perspective for efficient virtual-cache coherence. - Stefanos Kaxiras; Alberto Ros 001 (ISCA, 2013)

Introducing DVFS-Management in a Full-System Simulator. - Vasileios Spiliopoulos 001; Akash Bagdia; Andreas Hansson 001; Peter Aldworth; Stefanos Kaxiras (MASCOTS, 2013)

Efficient inter-core power and thermal balancing for multicore processors. - Juan M. Cebrian; Daniel Sánchez 004; Juan L. Aragón; Stefanos Kaxiras (Computing, 2013)

Fix the code. Don't tweak the hardware: A new compiler approach to Voltage-Frequency scaling. - Alexandra Jimborean; Konstantinos Koukos; Vasileios Spiliopoulos 001; David Black-Schaffer; Stefanos Kaxiras (CGO, 2014)

A tunable cache for approximate computing. - Magnus Själander; Nina Shariati Nilsson; Stefanos Kaxiras (NANOARCH, 2014)

Managing power constraints in a single-core scenario through power tokens. - Juan M. Cebrian; Daniel Sánchez 004; Juan L. Aragón; Stefanos Kaxiras (J. Supercomput., 2014)

Power-Efficient Computer Architectures: Recent Advances - Magnus Själander; Margaret Martonosi; Stefanos Kaxiras (Power-Efficient Computer Architectures, 2014)

An Efficient, Self-Contained, On-chip Directory: DIR1-SISD. - Mahdad Davari; Alberto Ros 001; Erik Hagersten; Stefanos Kaxiras (PACT, 2015)

Fast&Furious: A Tool for Detecting Covert Racing. - Alberto Ros 001; Stefanos Kaxiras (PARMA-DITAM@HiPEAC, 2015)

Hierarchical private/shared classification: The key to simple and efficient coherence for clustered cache hierarchies. - Alberto Ros 001; Mahdad Davari; Stefanos Kaxiras (HPCA, 2015)

Turning Centralized Coherence and Distributed Critical-Section Execution on their Head: A New Approach for Scalable Distributed Shared Memory. - Stefanos Kaxiras; David Klaftenegger; Magnus Norgren; Alberto Ros 001; Konstantinos Sagonas (HPDC, 2015)

Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed. - Andreas Sandberg; Nikos Nikoleris; Trevor E. Carlson; Erik Hagersten; Stefanos Kaxiras; David Black-Schaffer (IISWC, 2015)

The load slice core microarchitecture. - Trevor E. Carlson; Wim Heirman; Osman Allam; Stefanos Kaxiras; Lieven Eeckhout (ISCA, 2015)

Callback: efficient synchronization without invalidation with a directory just for spin-waiting. - Alberto Ros 001; Stefanos Kaxiras (ISCA, 2015)

The Effects of Granularity and Adaptivity on Private/Shared Classification for Coherence. - Mahdad Davari; Alberto Ros 001; Erik Hagersten; Stefanos Kaxiras (ACM Trans. Archit. Code Optim., 2015)

POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics. - Alberto Ros 001; Carl Leonardsson; Christos Sakalis; Stefanos Kaxiras (PACT, 2016)

Multiversioned decoupled access-execute: the key to energy-efficient compilation of general-purpose programs. - Konstantinos Koukos; Per Ekemark; Georgios Zacharopoulos; Vasileios Spiliopoulos 001; Stefanos Kaxiras; Alexandra Jimborean (CC, 2016)

Techniques for modulating error resilience in emerging multi-value technologies. - Magnus Själander; Gustaf Borgström; Mykhailo V. Klymenko; Françoise Remacle; Stefanos Kaxiras (Conf. Computing Frontiers, 2016)

Fencing Programs with Self-Invalidation and Self-Downgrade. - Parosh Aziz Abdulla; Mohamed Faouzi Atig; Stefanos Kaxiras; Carl Leonardsson; Alberto Ros 001; Yunyun Zhu (FORTE, 2016)

Splash-3: A properly synchronized benchmark suite for contemporary research. - Christos Sakalis; Carl Leonardsson; Stefanos Kaxiras; Alberto Ros 001 (ISPASS, 2016)

Racer: TSO consistency via race detection. - Alberto Ros 001; Stefanos Kaxiras (MICRO, 2016)

Profiling-Assisted Decoupled Access-Execute. - Jonatan Waern; Per Ekemark; Konstantinos Koukos; Stefanos Kaxiras; Alexandra Jimborean (CoRR, 2016)

Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead. - Konstantinos Koukos; Alberto Ros 001; Erik Hagersten; Stefanos Kaxiras (ACM Trans. Archit. Code Optim., 2016)

Exploring the Performance Limits of Out-of-order Commit. - Mehdi Alipour; Trevor E. Carlson; Stefanos Kaxiras (Conf. Computing Frontiers, 2017)

Automatic detection of extended data-race-free regions. - Alexandra Jimborean; Jonatan Waern; Per Ekemark; Stefanos Kaxiras; Alberto Ros 001 (CGO, 2017)

Clairvoyance: look-ahead compile-time scheduling. - Kim-Anh Tran; Trevor E. Carlson; Konstantinos Koukos; Magnus Själander; Vasileios Spiliopoulos 001; Stefanos Kaxiras; Alexandra Jimborean (CGO, 2017)

Non-Speculative Load-Load Reordering in TSO. - Alberto Ros 001; Trevor E. Carlson; Mehdi Alipour; Stefanos Kaxiras (ISCA, 2017)

A taxonomy of out-of-order instruction commit. - Mehdi Alipour; Trevor E. Carlson; Stefanos Kaxiras (ISPASS, 2017)

Addressing Energy Challenges in Filter Caches. - Ricardo Alves 001; Nikos Nikoleris; Stefanos Kaxiras; David Black-Schaffer (SBAC-PAD, 2017)

Transcending Hardware Limits with Software Out-of-Order Processing. - Trevor E. Carlson; Kim-Anh Tran; Alexandra Jimborean; Konstantinos Koukos; Magnus Själander; Stefanos Kaxiras (IEEE Comput. Archit. Lett., 2017)

Decoupled Access-Execute on ARM big.LITTLE. - Anton Weber; Kim-Anh Tran; Stefanos Kaxiras; Alexandra Jimborean (CoRR, 2017)

Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics. - Alberto Ros 001; Carl Leonardsson; Christos Sakalis; Stefanos Kaxiras (IEEE Trans. Parallel Distributed Syst., 2017)

Dynamically Disabling Way-prediction to Reduce Instruction Replay. - Ricardo Alves 001; Stefanos Kaxiras; David Black-Schaffer (ICCD, 2018)

Non-Speculative Store Coalescing in Total Store Order. - Alberto Ros 001; Stefanos Kaxiras (ISCA, 2018)

The Superfluous Load Queue. - Alberto Ros 001; Stefanos Kaxiras (MICRO, 2018)

SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order cores. - Kim-Anh Tran; Alexandra Jimborean; Trevor E. Carlson; Konstantinos Koukos; Magnus Själander; Stefanos Kaxiras (PLDI, 2018)

Mending Fences with Self-Invalidation and Self-Downgrade. - Parosh Aziz Abdulla; Mohamed Faouzi Atig; Stefanos Kaxiras; Carl Leonardsson; Alberto Ros 001; Yunyun Zhu (Log. Methods Comput. Sci., 2018)

Non-Speculative Load Reordering in Total Store Ordering. - Stefanos Kaxiras; Trevor E. Carlson; Mehdi Alipour; Alberto Ros 001 (IEEE Micro, 2018)

Static Instruction Scheduling for High Performance on Limited Hardware. - Kim-Anh Tran; Trevor E. Carlson; Konstantinos Koukos; Magnus Själander; Vasileios Spiliopoulos 001; Stefanos Kaxiras; Alexandra Jimborean (IEEE Trans. Computers, 2018)

Automatic Detection of Large Extended Data-Race-Free Regions with Conflict Isolation. - Alexandra Jimborean; Per Ekemark; Jonatan Waern; Stefanos Kaxiras; Alberto Ros 001 (IEEE Trans. Parallel Distributed Syst., 2018)

Ghost loads: what is the cost of invisible speculation? - Christos Sakalis; Mehdi Alipour; Alberto Ros 001; Alexandra Jimborean; Stefanos Kaxiras; Magnus Själander (CF, 2019)

FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors. - Mehdi Alipour; Rakesh Kumar 003; Stefanos Kaxiras; David Black-Schaffer (DATE, 2019)

Filter caching for free: the untapped potential of the store-buffer. - Ricardo Alves 001; Alberto Ros 001; David Black-Schaffer; Stefanos Kaxiras (ISCA, 2019)

Efficient invisible speculative execution through selective delay and value prediction. - Christos Sakalis; Stefanos Kaxiras; Alberto Ros 001; Alexandra Jimborean; Magnus Själander (ISCA, 2019)

Maximizing Limited Resources: a Limit-Based Study and Taxonomy of Out-of-Order Commit. - Mehdi Alipour; Trevor E. Carlson; David Black-Schaffer; Stefanos Kaxiras (J. Signal Process. Syst., 2019)

Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design. - Kim-Anh Tran; Christos Sakalis; Magnus Själander; Alberto Ros 001; Stefanos Kaxiras; Alexandra Jimborean (PACT, 2020)

Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors. - Mehdi Alipour; Stefanos Kaxiras; David Black-Schaffer; Rakesh Kumar 003 (HPCA, 2020)

Boosting Store Buffer Efficiency with Store-Prefetch Bursts. - Juan M. Cebrian; Stefanos Kaxiras; Alberto Ros 001 (MICRO, 2020)

Speculative Enforcement of Store Atomicity. - Alberto Ros 001; Stefanos Kaxiras (MICRO, 2020)

Evaluating the Potential Applications of Quaternary Logic for Approximate Computing. - Christos Sakalis; Alexandra Jimborean; Stefanos Kaxiras; Magnus Själander (ACM J. Emerg. Technol. Comput. Syst., 2020)

Understanding Selective Delay as a Method for Efficient Secure Speculative Execution. - Christos Sakalis; Stefanos Kaxiras; Alberto Ros 001; Alexandra Jimborean; Magnus Själander (IEEE Trans. Computers, 2020)

TSOPER: Efficient Coherence-Based Strict Persistency. - Per Ekemark; Yuan Yao 009; Alberto Ros 001; Konstantinos Sagonas; Stefanos Kaxiras (HPCA, 2021)

Splash-4: Improving Scalability with Lock-Free Constructs. - Eduardo José Gómez-Hernández; Ruixiang Shao; Christos Sakalis; Stefanos Kaxiras; Alberto Ros 001 (ISPASS, 2021)

ITSLF: Inter-Thread Store-to-Load Forwardingin Simultaneous Multithreading. - Josué Feliu; Alberto Ros 001; Manuel E. Acacio; Stefanos Kaxiras (MICRO, 2021)

Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations. - Eduardo José Gómez-Hernández; Juan M. Cebrian; J. Rubén Titos Gil; Stefanos Kaxiras; Alberto Ros 001 (MICRO, 2021)

Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation. - Christos Sakalis; Zamshed I. Chowdhury; Shayne Wadle; Ismail Akturk; Alberto Ros 001; Magnus Själander; Stefanos Kaxiras; Ulya R. Karpuzcu (SEED, 2021)

Seeds of SEED: Preventing Priority Inversion in Instruction Scheduling to Disrupt Speculative Interference. - Christos Sakalis; Magnus Själander; Stefanos Kaxiras (SEED, 2021)

Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions. - Pavlos Aimoniotis; Christos Sakalis; Magnus Själander; Stefanos Kaxiras (IEEE Comput. Archit. Lett., 2021)

On Value Recomputation to Accelerate Invisible Speculation. - Christos Sakalis; Zamshed I. Chowdhury; Shayne Wadle; Ismail Akturk; Alberto Ros 001; Magnus Själander; Stefanos Kaxiras; Ulya R. Karpuzcu (CoRR, 2021)

Selectively Delaying Instructions to Prevent Microarchitectural Replay Attacks. - Christos Sakalis; Stefanos Kaxiras; Magnus Själander (CoRR, 2021)

"It's a Trap!"-How Speculation Invariance Can Be Abused with Forward Speculative Interference. - Pavlos Aimoniotis; Christos Sakalis; Magnus Själander; Stefanos Kaxiras (CoRR, 2021)

Early Address Prediction: Efficient Pipeline Prefetch and Reuse. - Ricardo Alves 001; Stefanos Kaxiras; David Black-Schaffer (ACM Trans. Archit. Code Optim., 2021)

Clueless: A Tool Characterising Values Leaking as Addresses. - Xiaoyue Chen; Pavlos Aimoniotis; Stefanos Kaxiras (HASP@MICRO, 2022)

Splash-4: A Modern Benchmark Suite with Lock-Free Constructs. - Eduardo José Gómez-Hernández; Juan M. Cebrian; Stefanos Kaxiras; Alberto Ros 001 (IISWC, 2022)

Free atomics: hardware atomic operations without fences. - Ashkan Asgharzadeh; Juan M. Cebrian; Arthur Perais; Stefanos Kaxiras; Alberto Ros 001 (ISCA, 2022)

Data-Out Instruction-In (DOIN!): Leveraging Inclusive Caches to Attack Speculative Delay Schemes. - Pavlos Aimoniotis; Amund Bergland Kvalsvik; Magnus Själander; Stefanos Kaxiras (SEED, 2022)

Analysing software prefetching opportunities in hardware transactional memory. - Marina Shimchenko; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Manuel E. Acacio; Stefanos Kaxiras; Alberto Ros 001; Alexandra Jimborean (J. Supercomput., 2022)

Silent Stores in the Battery-less Internet of Things: A Good Idea? - Weining Song; Stefanos Kaxiras; Luca Mottola; Thiemo Voigt; Yuan Yao 009 (EWSN, 2023)

How addresses are made. - Xiaoyue Chen; Pavlos Aimoniotis; Stefanos Kaxiras (IISWC, 2023)

Doppelganger Loads: A Safe, Complexity-Effective Optimization for Secure Speculation Schemes. - Amund Bergland Kvalsvik; Pavlos Aimoniotis; Stefanos Kaxiras; Magnus Själander (ISCA, 2023)

ReCon: Efficient Detection, Management, and Use of Non-Speculative Information Leakage. - Pavlos Aimoniotis; Amund Bergland Kvalsvik; Xiaoyue Chen; Magnus Själander; Stefanos Kaxiras (MICRO, 2023)

Speculative inter-thread store-to-load forwarding in SMT architectures. - Josué Feliu; Alberto Ros 001; Manuel E. Acacio; Stefanos Kaxiras (J. Parallel Distributed Comput., 2023)

Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks. - Christos Sakalis; Stefanos Kaxiras; Magnus Själander (ACM Trans. Archit. Code Optim., 2023)

Bounding Speculative Execution of Atomic Regions to a Single Retry. - Eduardo José Gómez-Hernández; Juan M. Cebrian; Stefanos Kaxiras; Alberto Ros 001 (ASPLOS (4), 2024)

Hardware Cache Locking for All Memory Updates. - Ashkan Asgharzadeh; Eduardo José Gómez-Hernández; Juan M. Cebrian; Stefanos Kaxiras; Alberto Ros 001 (ICCD, 2024)

JANUS: A Simple and Efficient Speculative Defense using Reinforcement Learning. - Pavlos Aimoniotis; Stefanos Kaxiras (SBAC-PAD, 2024)

TangramFP: Energy-Efficient, Bit-Parallel, Multiply-Accumulate for Deep Neural Networks. - Yuan Yao 009; Xiaoyue Chen; Hannah Atmer; Stefanos Kaxiras (SBAC-PAD, 2024)

A First Exploration of Fine-Grain Coherence for Integrity Metadata. - Per Ekemark; Alberto Ros 001; Konstantinos Sagonas; Stefanos Kaxiras (SEED, 2024)

TaDA: Task Decoupling Architecture for the Battery-less Internet of Things. - Weining Song; Stefanos Kaxiras; Thiemo Voigt; Yuan Yao 009; Luca Mottola (SenSys, 2024)

No Rush in Executing Atomic Instructions. - Ashkan Asgharzadeh; Josué Feliu; Manuel E. Acacio; Stefanos Kaxiras; Alberto Ros 001 (HPCA, 2025)

RXT: RefleXive Address Translation for Pointer-Chasing Workloads. - Rashid Aligholipour; Pavlos Aimoniotis; Stefanos Kaxiras; Yuan Yao 009 (IPDPS, 2025)