Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip. - Manolis Katevenis; Stefanos Sidiropoulos; Costas Courcoubetis (IEEE J. Sel. Areas Commun., 1991)

A speed, power, and supply noise evaluation of ECL driver circuits. - Norman P. Jouppi; Stefanos Sidiropoulos; Suresh Menon (IEEE J. Solid State Circuits, 1996)

A 700-Mb/s/pin CMOS signaling interface using current integrating receivers. - Stefanos Sidiropoulos; Mark Horowitz (IEEE J. Solid State Circuits, 1997)

A semidigital dual delay-locked loop. - Stefanos Sidiropoulos; Mark A. Horowitz (IEEE J. Solid State Circuits, 1997)

High-speed electrical signaling: overview and limitations. - Mark Horowitz; Chih-Kong Ken Yang; Stefanos Sidiropoulos (IEEE Micro, 1998)

A variable-frequency parallel I/O interface with adaptive power-supply regulation. - Gu-Yeon Wei; Jaeha Kim; Dean Liu; Stefanos Sidiropoulos; Mark A. Horowitz (IEEE J. Solid State Circuits, 2000)

A Framework for Designing Reusable Analog Circuits. - Dean Liu; Stefanos Sidiropoulos; Mark Horowitz (ICCAD, 2003)

A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs. - Kun-Yung Ken Chang; Jason Wei; Charlie Huang; Simon Li; Kevin S. Donnelly; Mark Horowitz; Yingxuan Li; Stefanos Sidiropoulos (IEEE J. Solid State Circuits, 2003)

Improving CDR Performance via Estimation. - Haechang Lee; Akash Bansal; Yohan Frans; Jared Zerbe; Stefanos Sidiropoulos; Mark Horowitz (ISSCC, 2006)

An integrated VCSEL driver for 10Gb ethernet in 0.13µm CMOS. - Shahriar Rabii; Nikhil Acharya; Pak Chau; Joseph Dao; Arnold Feldman; Haw-Jyh Liaw; Dean Liu; Marc Loinaz; Manuel Luschas; Azmeer Salleh; Siddharth Sheth; Stefanos Sidiropoulos; et al. (ISSCC, 2006)

A 10.3GS/s 6b flash ADC for 10G Ethernet applications. - Shwetabh Verma; Athos Kasapi; Li-min Lee; Dean Liu; Dimitri Loizos; Song-Hee Paik; Aida Varzaghani; Sotirios Zogopoulos; Stefanos Sidiropoulos (ISSCC, 2013)

A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications. - Aida Varzaghani; Athos Kasapi; Dimitri Loizos; Song-Hee Paik; Shwetabh Verma; Sotirios Zogopoulos; Stefanos Sidiropoulos (IEEE J. Solid State Circuits, 2013)

A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET. - Aida Varzaghani; Bardia Bozorgzadeh; Jack Lam; Ankush Goel; Xiaobin Yuan; Mohamed Elzeftawi; Mehran Izad; Sudipta Sarkar; Alberto Baldisserotto; Seong-Ryong Ryu; Steven Mikes; Jeffrey Hwang; et al. (VLSI Technology and Circuits, 2022)