Testability of path history memories with register-exchange architecture used in Viterbi-decoders. - Stefan R. Meier; Mario Steinert; Steffen Buch (ISCAS (3), 2002)

Low power register file architecture for application specific DSPs. - Matthias Müller 002; Andreas Wortmann 002; Sven Simon 001; S. Wolter; Steffen Buch; Marek Wróblewski; Josef A. Nossek (ISCAS (4), 2002)

An instruction set for the efficient implementation of the CORDIC algorithm. - Sven Simon 001; Matthias Müller 002; Holger Gryska; Andreas Wortmann 002; Steffen Buch (ISCAS (2), 2004)

Low power synthesizable register files for processor and IP cores. - Matthias Müller 002; Sven Simon 001; Holger Gryska; Andreas Wortmann 002; Steffen Buch (Integr., 2006)

A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions. - Thomas Lüftner; Jörg Berthold; Christian Pacha; Georg Georgakos; Guillaume Sauzon; Olaf Hömke; Jurij Beshenar; Peter Mahrla; Knut M. Just; Peter Hober; Stephan Henzler; Doris Schmitt-Landsiedel; et al. (IEEE J. Solid State Circuits, 2007)

Error Detecting and Correcting Codes for DRAM Functional Safety. - Steffen Buch (MEMSYS, 2023)