Integrated Temporal Planning, Module Selection and Placement of Tasks for Dynamic Networks-on-Chip. - Philipp Mahr; Steffen Christgau; Christian Haubelt; Christophe Bobda (IPDPS Workshops, 2011)

The Benefit of Topology Awareness of MPI Applications on the SCC. - Steffen Christgau; Simon Kiertscher; Bettina Schnor (MARC Symposium, 2011)

Awareness of MPI Virtual Process Topologies on the Single-Chip Cloud Computer. - Steffen Christgau; Bettina Schnor (IPDPS Workshops, 2012)

One-Sided Communication in RCKMPI for the Single-Chip Cloud Computer. - Steffen Christgau; Bettina Schnor (MARC Symposium, 2012)

A comparison of CUDA and OpenACC: Accelerating the Tsunami Simulation EasyWave. - Steffen Christgau; Johannes Spazier; Bettina Schnor; Martin Hammitzsch; Andrey Y. Babeyko; Joachim Waechter (ARCS Workshops, 2014)

Automatic generation of parallel C code for stencil applications written in MATLAB. - Johannes Spazier; Steffen Christgau; Bettina Schnor (ARRAY@PLDI, 2016)

Software-managed Cache Coherence for fast One-Sided Communication. - Steffen Christgau; Bettina Schnor (PMAM@PPoPP, 2016)

Efficient Parallelization of MATLAB Stencil Applications for Multi-core Clusters. - Johannes Spazier; Steffen Christgau; Bettina Schnor (WOLFHPC@SC, 2016)

Exploring one-sided communication and synchronization on a non-cache-coherent many-core architecture. - Steffen Christgau; Bettina Schnor (Concurr. Comput. Pract. Exp., 2017)

One-sided communication on a non-cache-coherent many-core architecture (Einseitige Kommunikation auf einer nicht-cache-kohärenten Vielkern-Prozessorarchitektur) - Steffen Christgau (2017)

Porting a Legacy CUDA Stencil Code to oneAPI. - Steffen Christgau; Thomas Steinke 001 (IPDPS Workshops, 2020)

Leveraging a Heterogeneous Memory System for a Legacy Fortran Code: The Interplay of Storage Class Memory, DRAM and OS. - Steffen Christgau; Thomas Steinke 001 (MCHPC@SC, 2020)

A First Step towards Support for MPI Partitioned Communication on SYCL-programmed FPGAs. - Steffen Christgau; Marius Knaust; Thomas Steinke 001 (H2RC@SC, 2022)

Enabling Communication with FPGA-based Network-attached Accelerators for HPC Workloads. - Steffen Christgau; Dylan Everingham; Florian Mikolajczak; Niklas Schelten; Bettina Schnor; Max Schrötter; Benno Stabernack; Fritjof Steinert (SC Workshops, 2023)

Gaining Cross-Platform Parallelism for HAL's Molecular Dynamics Package using SYCL. - Viktor Skoblin; Felix Höfling; Steffen Christgau (CoRR, 2024)

On the Usability and Energy Efficiency of High-Level Synthesis for FPGA-based Network-Attached Accelerators. - Steffen Christgau; Dylan Everingham; Max Lübke; Marco De Lucia; Danny Puhan; Niklas Schelten; Bettina Schnor; Hannes Signer; Johannes Spazier; Benno Stabernack; Fritjof Steinert; Serhii Yahdzhyiev (IPDPS (Workshops), 2025)