Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes. - Marcos B. S. Tavares; Steffen Kunze; Emil Matús; Gerhard P. Fettweis (ASAP, 2008)

A dual-core programmable decoder for LDPC convolutional codes. - Marcos B. S. Tavares; Emil Matús; Steffen Kunze; Gerhard P. Fettweis (ISCAS, 2008)

ASIP Decoder Architecture for Convolutional and LDPC Codes. - Steffen Kunze; Emil Matús; Gerhard P. Fettweis (ISCAS, 2009)

Combining LDPC, turbo and Viterbi decoders: Benefits and costs. - Steffen Kunze; Emil Matús; Gerhard P. Fettweis; Tomoyoshi Kobori (SiPS, 2011)

A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates. - Markus Winter 002; Steffen Kunze; Esther P. Adeva; Björn Mennenga; Emil Matús; Gerhard P. Fettweis; Holger Eisenreich; Georg Ellguth; Sebastian Höppner; Stefan Scholze; René Schüffny; Tomoyoshi Kobori (ISSCC, 2012)

On the design and implementation of multi-mode channel decoders. - Steffen Kunze (Vogt, 2013)

10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS. - Benedikt Noethen; Oliver Arnold; Esther P. Adeva; Tobias Seifert; Erik Fischer; Steffen Kunze; Emil Matús; Gerhard P. Fettweis; Holger Eisenreich; Georg Ellguth; Stephan Hartmann 002; Sebastian Höppner; et al. (ISSCC, 2014)