EASY - ein Werkzeug zur Unterstützung der automatischen High-Level-Synthese des Datenteils digitaler Systeme: Konzeption und Implementierung einer Experimentalversion. - Steffen Rülke (1990)

Low Power Design of FSMs by State Assignment and Disabling Self-Loops. - Manfred Koegst; Günter Franke; Steffen Rülke; Klaus Feske (EUROMICRO, 1997)

Multi-Criterial State Assignment for Low Power FSM Design. - Manfred Koegst; Günter Franke; Steffen Rülke; Klaus Feske (EUROMICRO, 1998)

FPGA based prototyping using a target driven FSM partitioning strategy. - Klaus Feske; Steffen Rülke; Manfred Koegst (ICECS, 1998)

Verringerung der Leistungsaufnahme in sequentiellen Schaltungen durch Vorlogik und zweistufige Zustandskodierung. - Manfred Koegst; Günter Franke; Klaus Feske; Steffen Rülke (MBMV, 1998)

Two-Criterial Constraint-Driven FSM State Encoding for Low Power. - Manfred Koegst; Steffen Rülke; Günter Franke; Maria J. Avedillo (DSD, 2001)

Enhanced Reusability for SoC-Based HW/SW Co-Design. - Maik Boden; Jörg Schneider; Klaus Feske; Steffen Rülke (DSD, 2002)

Use of HDL Code Checkers to Support the IP Entrance Check - A Requirement Analysis. - Ronny Frevert; Steffen Rülke; Torsten Schäfer; Frank Dresig (DSD, 2002)

Eine wiederverwendungsgerechte Entwurfsmethodik für rekonfigurierbare SoC-Architekturen. - Jörg Schneider; Maik Boden; Steffen Rülke (MBMV, 2002)

Cost-Efficient Implementation of Adaptive Finite State Machines. - Maik Boden; Manfred Koegst; José Luis Tiburcio Badía; Steffen Rülke (DSD, 2004)

IPQ: IP Qualification for Efficient System Design. - Hans-Jürgen Brand; Steffen Rülke; Martin Radetzki (ISQED, 2004)

Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment. - Jörg Schneider; Vincent Kotzsch; Steffen Rülke (PARELEC, 2004)

A Low-Cost Realization of an Adaptable Protocol Processing Unit. - Maik Boden; Alex Gleich; Steffen Rülke; Ulrich Nageldinger (IPDPS, 2005)

Non-Intrusive High-level SystemC Debugging. - Frank Rogin; Erhard Fehlauer; Steffen Rülke; Sebastian Ohnewald; Thomas Berndt (FDL, 2006)

A high-level target-precise model for designing reconfigurable HW tasks. - Maik Boden; Steffen Rülke; Jürgen Becker 001 (IPDPS, 2006)

A Run-Time Scheduling Framework for a Reconfigurable Hardware Emulator. - Rene Beckert; Thomas Fuchs 003; Steffen Rülke; Wolfram Hardt (DSD, 2007)

An Integrated SystemC Debugging Environment. - Frank Rogin; Christian Genz; Rolf Drechsler; Steffen Rülke (FDL, 2007)

High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs. - Maik Boden; Thomas Fiebig; Torsten Meibner; Steffen Rülke; Jürgen Becker 001 (IPDPS, 2007)

A Tailored Design Partitioning Method for Hardware Emulation. - Rene Beckert; Thomas Fuchs 003; Steffen Rülke; Wolfram Hardt (IEEE International Workshop on Rapid System Prototyping, 2007)

Automatic Generation of Complex Properties for Hardware Designs. - Frank Rogin; Thomas Klotz; Görschwin Fey; Rolf Drechsler; Steffen Rülke (DATE, 2008)

GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs. - Maik Boden; Thomas Fiebig; Markus Reiband; Peter Reichel; Steffen Rülke (ISVLSI, 2008)

Automatic debugging of System-on-a-Chip designs. - Frank Rogin; Rolf Drechsler; Steffen Rülke (SoCC, 2009)

Advanced verification by automatic property generation. - Frank Rogin; Thomas Klotz; Görschwin Fey; Rolf Drechsler; Steffen Rülke (IET Comput. Digit. Tech., 2009)

Bounded model checking of Contiki applications. - Thilo Vörtler; Steffen Rülke; Petra Hofstedt (DDECS, 2012)