Ultra low cost asynchronous handshake checker. - Steffen Zeidler 001; Marcus Ehrig; Milos Krstic; Michael Augustin; Christoph Wolf; Rolf Kraemer (IOLTS, 2009)

On-line testing of bundled-data asynchronous handshake protocols. - Steffen Zeidler 001; Alexandre V. Bystrov; Milos Krstic; Rolf Kraemer (IOLTS, 2010)

An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis. - Oliver Schrape; Frank Winkler 001; Steffen Zeidler 001; Markus Petri; Eckhard Grass; Ulrich Jagdhold (PATMOS, 2010)

Design of a Test Processor for Asynchronous Chip Test. - Steffen Zeidler 001; Christoph Wolf; Milos Krstic; Frank Vater; Rolf Kraemer (Asian Test Symposium, 2011)

Overview on ATE Test and Debugging Methods for Asynchronous Circuits. - Christoph Wolf; Steffen Zeidler 001; Milos Krstic; Rolf Kraemer (MTV, 2011)

Functional Pattern Generation for Asynchronous Designs in a Test Processor Environment. - Steffen Zeidler 001; Christoph Wolf; Milos Krstic; Rolf Kraemer (Asian Test Symposium, 2012)

Asynchronous circuit design: From basics to practical applications. - Eckhard Grass; Milos Krstic; Xin Fan 003; Steffen Zeidler 001 (DDECS, 2012)

Design of a low-power asynchronous elliptic curve cryptography coprocessor. - Steffen Zeidler 001; Michael Goderbauer; Milos Krstic (ICECS, 2013)

Enabling functional tests of asynchronous circuits using a test processor solution. - Steffen Zeidler 001 (2013)

A Design Preconditioning Flow for Low-Noise Circuits. - Steffen Zeidler 001; Xin Fan 003; Oliver Schrape; Milos Krstic (DDECS, 2015)

A survey about testing asynchronous circuits. - Steffen Zeidler 001; Milos Krstic (ECCTD, 2015)

GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits. - Milan Babic; Steffen Zeidler 001; Milos Krstic (ASYNC, 2016)

An Early Stage Design Flow for Switching Noise Attenuation. - Steffen Zeidler 001; Xin Fan 003; Oliver Schrape; Milos Krstic (J. Circuits Syst. Comput., 2016)

Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling. - Xin Fan 003; Mikkel B. Stegmann; Oliver Schrape; Steffen Zeidler 001; Isac G. Jensen; Jannich Thorsen; Tobias Bjerregaard; Milos Krstic (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Aspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-Flops. - Oliver Schrape; Anselm Breitenreiter; Steffen Zeidler 001; Milos Krstic (DSD, 2019)

Selective Fault Tolerance by Counting Gates with Controlling Value. - Anselm Breitenreiter; Stefan Weidling; Oliver Schrape; Steffen Zeidler 001; Pedro Reviriego; Milos Krstic (IOLTS, 2019)

A Glitch-free Clock Multiplexer for Non-Continuously Running Clocks. - Steffen Zeidler 001; Oliver Schrape; Anselm Breitenreiter; Milos Krstic (DSD, 2020)

Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops. - Oliver Schrape; Anselm Breitenreiter; Carsten Schulze; Steffen Zeidler 001; Milos Krstic (LASCAS, 2021)

Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops. - Oliver Schrape; Marko S. Andjelkovic; Anselm Breitenreiter; Steffen Zeidler 001; Alexey Balashov; Milos Krstic (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)