Improving Test Pattern Compactness in SAT-based ATPG. - Stephan Eggersglüß; Rolf Drechsler (ATS, 2007)

SAT-based ATPG for Path Delay Faults in Sequential Circuits. - Stephan Eggersglüß; Görschwin Fey; Rolf Drechsler (ISCAS, 2007)

Experimental Studies on SAT-Based ATPG for Gate Delay Faults. - Stephan Eggersglüß; Daniel Tille; Görschwin Fey; Rolf Drechsler; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel (ISMVL, 2007)

Formal Verification on the Word Level using SAT-like Proof Techniques. - Görschwin Fey; Daniel Große; Stephan Eggersglüß; Robert Wille; Rolf Drechsler (MBMV, 2007)

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. - Stephan Eggersglüß; Görschwin Fey; Rolf Drechsler; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel (MEMOCODE, 2007)

SWORD: A SAT like Prover Using Word Level Information. - Robert Wille; Görschwin Fey; Daniel Große; Stephan Eggersglüß; Rolf Drechsler (VLSI-SoC (Selected Papers), 2007)

SAT-based Automatic Test Pattern Generation. - Rolf Drechsler; Stephan Eggersglüß; Görschwin Fey; Daniel Tille (Evolutionary Test Generation, 2008)

On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. - Stephan Eggersglüß; Rolf Drechsler (ISMVL, 2008)

On Acceleration of SAT-Based ATPG for Industrial Designs. - Rolf Drechsler; Stephan Eggersglüß; Görschwin Fey; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel; Daniel Tille (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Test Pattern Generation using Boolean Proof Engines. - Rolf Drechsler; Stephan Eggersglüß; Görschwin Fey; Daniel Tille (Springer, 2009)

Speeding up SAT-Based ATPG Using Dynamic Clause Activation. - Stephan Eggersglüß; Daniel Tille; Rolf Drechsler (Asian Test Symposium, 2009)

Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. - Stephan Eggersglüß; Rolf Drechsler (ETS, 2009)

Timing Arc based logic analysis for false noise reduction. - Murthy Palla; Jens Bargfrede; Stephan Eggersglüß; Walter Anheier; Rolf Drechsler (ICCAD, 2009)

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). - Rolf Drechsler; Stephan Eggersglüß; Görschwin Fey; Jürgen Schlöffel; Daniel Tille (it Inf. Technol., 2009)

Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. - Daniel Tille; Stephan Eggersglüß; Rene Krenz-Baath; Jürgen Schlöffel; Rolf Drechsler (ETS, 2010)

Robuste Erfüllbarkeitsalgorithmen zur Generierung hochwertiger Testmuster für digitale Schaltungen. - Stephan Eggersglüß (Ausgezeichnete Informatikdissertationen, 2010)

Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation. - Stephan Eggersglüß; Daniel Tille; Rolf Drechsler (ISCAS, 2010)

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. - Stephan Eggersglüß; Görschwin Fey; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel; Rolf Drechsler (J. Electron. Test., 2010)

Incremental Solving Techniques for SAT-based ATPG. - Daniel Tille; Stephan Eggersglüß; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Robust algorithms for high quality test pattern generation using Boolean satisfiability. - Stephan Eggersglüß (2010)

As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization. - Stephan Eggersglüß; Rolf Drechsler (DATE, 2011)

Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application. - Stephan Eggersglüß; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

High Quality Test Pattern Generation and Boolean Satisfiability. - Stephan Eggersglüß; Rolf Drechsler (Springer, 2012)

Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization. - Stephan Eggersglüß; Mahmut Yilmaz; Krishnendu Chakrabarty (Asian Test Symposium, 2012)

A new SAT-based ATPG for generating highly compacted test sets. - Stephan Eggersglüß; Rene Krenz-Baath; Andreas Glowatz; Friedrich Hapke; Rolf Drechsler (DDECS, 2012)

A Highly Fault-Efficient SAT-Based ATPG Flow. - Stephan Eggersglüß; Rolf Drechsler (IEEE Des. Test Comput., 2012)

Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill. - Stephan Eggersglüß (Asian Test Symposium, 2013)

Improved SAT-based ATPG: more constraints, better compaction. - Stephan Eggersglüß; Robert Wille; Rolf Drechsler (ICCAD, 2013)

PASSAT 2.0: A multi-functional SAT-based testing framework. - Rolf Drechsler; Melanie Diepenbeck; Stephan Eggersglüß; Robert Wille (LATW, 2013)

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization. - Bernd Becker 001; Rolf Drechsler; Stephan Eggersglüß; Matthias Sauer 002 (DTIS, 2014)

Optimization-based multiple target test generation for highly compacted test sets. - Stephan Eggersglüß; Kenneth Schmitz; Rene Krenz-Baath; Rolf Drechsler (ETS, 2014)

Automated formal verification of X propagation with respect to testability issues. - Mehdi Dehbashi; Daniel Tille; Ulrike Pfannkuchen; Stephan Eggersglüß (IDT, 2014)

Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets. - Stephan Eggersglüß (J. Electron. Test., 2014)

An effective fault ordering heuristic for SAT-based dynamic test compaction techniques. - Stephan Eggersglüß; Rolf Drechsler (it Inf. Technol., 2014)

Compact test set generation for test compression-based designs. - Stephan Eggersglüß (ETS, 2015)

Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test. - Stephan Eggersglüß; Stefan Holst; Daniel Tille; Kohei Miyase; Xiaoqing Wen (ATS, 2016)

SAT-based post-processing for regional capture power reduction in at-speed scan test generation. - Stephan Eggersglüß; Kohei Miyase; Xiaoqing Wen (ETS, 2016)

VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers. - Sebastian Huhn 001; Stephan Eggersglüß; Rolf Drechsler (ETS, 2016)

Exploring superior structural materials using multi-objective optimization and formal techniques. - Rolf Drechsler; Stephan Eggersglüß; Nils Ellendt; Sebastian Huhn 001; Lutz Mädler (ISED, 2016)

On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets. - Stephan Eggersglüß; Kenneth Schmitz; Rene Krenz-Baath; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Identification of Efficient Clustering Techniques for Test Power Activity on the Layout. - Harshad Dhotre; Stephan Eggersglüß; Rolf Drechsler (ATS, 2017)

Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. - Sebastian Huhn 001; Stephan Eggersglüß; Krishnendu Chakrabarty; Rolf Drechsler (DATE, 2017)

Machine learning based test pattern analysis for localizing critical power activity areas. - Harshad Dhotre; Stephan Eggersglüß; Mehdi Dehbashi; Ulrike Pfannkuchen; Rolf Drechsler (DFT, 2017)

Reconfigurable TAP controllers with embedded compression for large test data volume. - Sebastian Huhn 001; Stephan Eggersglüß; Rolf Drechsler (DFT, 2017)

Foreword. - Maria K. Michael; Rolf Drechsler; Stephan Eggersglüß; Haralampos-G. D. Stratigopoulos; Sybille Hellebrand; Rob Aitken (ETS, 2017)

Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements. - Sebastian Huhn 001; Heike Sonnenberg; Stephan Eggersglüß; Brigitte Clausen; Rolf Drechsler (SSCI, 2017)

Approximation-aware testing for approximate circuits. - Arun Chandrasekharan; Stephan Eggersglüß; Daniel Große; Rolf Drechsler (ASP-DAC, 2018)

Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing. - Harshad Dhotre; Stephan Eggersglüß; Rolf Drechsler; Mehdi Dehbashi; Ulrike Pfannkuchen (DDECS, 2018)

Machine Learning-based Prediction of Test Power. - Harshad Dhotre; Stephan Eggersglüß; Krishnendu Chakrabarty; Rolf Drechsler (ETS, 2019)

Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques. - Stephan Eggersglüß (ITC, 2019)

IEEE European Test Symposium (ETS). - Stephan Eggersglüß; Said Hamdioui; Artur Jutman; Maria K. Michael; Jaan Raik; Matteo Sonza Reorda; Mehdi Baradaran Tahoori; Elena-Ioana Vatajelu (ITC, 2019)

Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements. - Harshad Dhotre; Stephan Eggersglüß; Rolf Drechsler (LATS, 2019)

On Reduction of Deterministic Test Pattern Sets. - Stephan Eggersglüß; Sylwester Milewski; Janusz Rajski; Jerzy Tyszer (ITC, 2021)

A New Static Compaction of Deterministic Test Sets. - Stephan Eggersglüß; Sylwester Milewski; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Cell-aware Transistor State Stress Model and its Application for Quality Measurement. - Stephan Eggersglüß; Andreas Glowatz (ITC, 2024)

The Future of Design for Test and Silicon Lifecycle Management. - Janusz Rajski; Vivek Chickermane; Jean-François Côté; Stephan Eggersglüß; Nilanjan Mukherjee 001; Jerzy Tyszer (IEEE Des. Test, 2024)