Stephan Hartmann

Orcid: 0000-0001-5227-6533

Affiliations:

TU Dresden, Germany

According to our database¹, Stephan Hartmann authored at least 17 papers between 2010 and 2021.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

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PhD thesis

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Bibliography

2021

Hardware Implementation of an OPC UA Server for Industrial Field Devices.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing.

[BibT_eX]

[DOI]

CoRR, 2021

2019

Dynamic Power Management for Neuromorphic Many-Core Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

2017

Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System.

[BibT_eX]

[DOI]

CoRR, 2017

Pattern representation and recognition with accelerated analog neuromorphic systems.

[BibT_eX]

[DOI]

CoRR, 2017

Pattern representation and recognition with accelerated analog neuromorphic systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Dynamic voltage and frequency scaling for neuromorphic many-core systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

An MPSoC for energy-efficient database query processing.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

2014

10.7 A 105GOPS 36mm<sup>2</sup> heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012

Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system.

[BibT_eX]

[DOI]

Marc-Olivier Schwartz

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Dedicated FPGA communication architecture and design for a large-scale neuromorphic system.

[BibT_eX]

[DOI]

Vasilis N. Thanasoulis

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

Live demonstration: Packet-based AER with 3Gevent/s cumulative throughput.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

Stephan Hartmann

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