Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput. - Stephan Hartmann 002; Stefan Schiefer; Stefan Scholze; Johannes Partzsch; Christian Mayr 001; Stephan Henker; René Schüffny (ICECS, 2010)

Live demonstration: Packet-based AER with 3Gevent/s cumulative throughput. - Stefan Schiefer; Stephan Hartmann 002; Stefan Scholze; Johannes Partzsch; Christian Mayr 001; Stephan Henker; René Schüffny (ISCAS, 2011)

Dedicated FPGA communication architecture and design for a large-scale neuromorphic system. - Vasilis N. Thanasoulis; Johannes Partzsch; Stephan Hartmann 002; Christian Mayr 001; René Schüffny (ICECS, 2012)

Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system. - Johannes Schemmel; Andreas Grübl; Stephan Hartmann 002; Alexander Kononov; Christian Mayr 001; Karlheinz Meier; Sebastian Millner; Johannes Partzsch; Stefan Schiefer; Stefan Scholze; René Schüffny; Marc-Olivier Schwartz (ISCAS, 2012)

10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS. - Benedikt Noethen; Oliver Arnold; Esther P. Adeva; Tobias Seifert; Erik Fischer; Steffen Kunze; Emil Matús; Gerhard P. Fettweis; Holger Eisenreich; Georg Ellguth; Stephan Hartmann 002; Sebastian Höppner; et al. (ISSCC, 2014)

An MPSoC for energy-efficient database query processing. - Sebastian Haas; Oliver Arnold; Benedikt Nöthen; Stefan Scholze; Georg Ellguth; Andreas Dixius; Sebastian Höppner; Stefan Schiefer; Stephan Hartmann 002; Stephan Henker; Thomas Hocker; Jörg Schreiter; et al. (DAC, 2016)

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications. - Sebastian Haas; Tobias Seifert; Benedikt Nöthen; Stefan Scholze; Sebastian Höppner; Andreas Dixius; Esther Pérez Adeva; Thomas R. Augustin; Friedrich Pauls; Sadia Moriam; Mattis Hasler; Erik Fischer; et al. (DAC, 2017)

Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system. - Sebastian Schmitt; Johann Klähn; Guillaume Bellec; Andreas Grübl; Maurice Güttler; Andreas Hartel; Stephan Hartmann 002; Dan Husmann de Oliveira; Kai Husmann; Sebastian Jeltsch; Vitali Karasenko; Mitja Kleider; et al. (IJCNN, 2017)

Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems. - Sebastian Höppner; Yexin Yan; Bernhard Vogginger; Andreas Dixius; Johannes Partzsch; Prateek Joshi; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Stefan Scholze; Georg Ellguth; Love Cederstroem; et al. (ISCAS, 2017)

Dynamic voltage and frequency scaling for neuromorphic many-core systems. - Sebastian Höppner; Yexin Yan; Bernhard Vogginger; Andreas Dixius; Johannes Partzsch; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Stefan Scholze; Georg Ellguth; Love Cederstroem; Matthias Eberlein; et al. (ISCAS, 2017)

Pattern representation and recognition with accelerated analog neuromorphic systems. - Mihai A. Petrovici; Sebastian Schmitt; Johann Klähn; Robert D. St. Louis; Anna Schroeder; Guillaume Bellec; Johannes Bill; Oliver Breitwieser; Ilja Bytschok; Andreas Grübl; Maurice Güttler; Andreas Hartel; et al. (ISCAS, 2017)

Pattern representation and recognition with accelerated analog neuromorphic systems. - Mihai A. Petrovici; Sebastian Schmitt; Johann Klähn; David Stöckel; Anna Schroeder; Guillaume Bellec; Johannes Bill; Oliver Breitwieser; Ilja Bytschok; Andreas Grübl; Maurice Güttler; Andreas Hartel; et al. (CoRR, 2017)

Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System. - Sebastian Schmitt; Johann Klaehn; Guillaume Bellec; Andreas Grübl; Maurice Guettler; Andreas Hartel; Stephan Hartmann 002; Dan Husmann de Oliveira; Kai Husmann; Vitali Karasenko; Mitja Kleider; Christoph Koke; et al. (CoRR, 2017)

Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS. - Florian Protze; Martin Kreißig; Frank Ellinger; Sebastian Höppner; Stephan Hartmann 002; Stefan Hänzsche; Stefan Scholze; Georg Ellguth; Christian Mayr 001 (VLSI-SoC, 2019)

Dynamic Power Management for Neuromorphic Many-Core Systems. - Sebastian Höppner; Bernhard Vogginger; Yexin Yan; Andreas Dixius; Stefan Scholze; Johannes Partzsch; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Georg Ellguth; Love Cederstroem; Luis A. Plana; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing. - Sebastian Höppner; Yexin Yan; Andreas Dixius; Stefan Scholze; Johannes Partzsch; Marco Stolba; Florian Kelber; Bernhard Vogginger; Felix Neumärker; Georg Ellguth; Stephan Hartmann 002; Stefan Schiefer; et al. (CoRR, 2021)

Hardware Implementation of an OPC UA Server for Industrial Field Devices. - Heiner Bauer; Sebastian Höppner; Chris Paul Iatrou; Zohra Charania; Stephan Hartmann 002; Saif-Ur Rehman; Andreas Dixius; Georg Ellguth; Dennis Walter; Johannes Uhlig; Felix Neumärker; Marc Berthel; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2021)