Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes. - Stephan Henzler; Markus Koban; Doris Schmitt-Landsiedel; Jörg Berthold; Georg Georgakos (VLSI-SOC, 2003)

Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes. - Stephan Henzler; Philip Teichmann; Markus Koban; Jörg Berthold; Georg Georgakos; Doris Schmitt-Landsiedel (VLSI-SoC (Selected Papers), 2003)

Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption. - Stephan Henzler; Georg Georgakos; Jörg Berthold; Doris Schmitt-Landsiedel (PATMOS, 2004)

Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits. - Stephan Henzler; Georg Georgakos; Jörg Berthold; Doris Schmitt-Landsiedel (PATMOS, 2004)

Making adiabatic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode circuits. - Stephan Henzler; Thomas Nirschl; Matthias Eireiner; Ettore Amirante; Doris Schmitt-Landsiedel (Conf. Computing Frontiers, 2005)

Impact of process parameter variations on the energy dissipation in adiabatic logic. - Jürgen Fischer; Ettore Amirante; Thomas Nirschl; Philip Teichmann; Stephan Henzler; Doris Schmitt-Landsiedel (ECCTD, 2005)

Dynamic state-retention flip flop for fine-grained sleep-transistor scheme. - Stephan Henzler; Thomas Nirschi; Christian Pacha; Peter Spindler; Philip Teichmann; Michael Fulde; Jürgen Fischer; Matthias Eireiner; Thomas Fischer; Georg Georgakos; Jörg Berthold; Doris Schmitt-Landsiedel (ESSCIRC, 2005)

Power-Clock Gating in Adiabatic Logic Circuits. - Philip Teichmann; Jürgen Fischer; Stephan Henzler; Ettore Amirante; Doris Schmitt-Landsiedel (PATMOS, 2005)

High-speed low-power frequency divider with intrinsic phase rotator. - Stephan Henzler; Siegmar Koeppe (ISLPED, 2006)

A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions. - Thomas Lüftner; Jörg Berthold; Christian Pacha; Georg Georgakos; Guillaume Sauzon; Olaf Hömke; Jurij Beshenar; Peter Mahrla; Knut M. Just; Peter Hober; Stephan Henzler; Doris Schmitt-Landsiedel; et al. (ISSCC, 2006)

Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead. - Stephan Henzler; Georg Georgakos; Matthias Eireiner; Thomas Nirschl; Christian Pacha; Jörg Berthold; Doris Schmitt-Landsiedel (IEEE J. Solid State Circuits, 2006)

Variation tolerant high resolution and low latency time-to-digital converter. - Stephan Henzler; Siegmar Koeppe; Dominik Lorenz; Winfried Kamp; Ronald Kuenemund; Doris Schmitt-Landsiedel (ESSCIRC, 2007)

In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations. - Matthias Eireiner; Stephan Henzler; Georg Georgakos; Jörg Berthold; Doris Schmitt-Landsiedel (IEEE J. Solid State Circuits, 2007)

A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions. - Thomas Lüftner; Jörg Berthold; Christian Pacha; Georg Georgakos; Guillaume Sauzon; Olaf Hömke; Jurij Beshenar; Peter Mahrla; Knut M. Just; Peter Hober; Stephan Henzler; Doris Schmitt-Landsiedel; et al. (IEEE J. Solid State Circuits, 2007)

90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization. - Stephan Henzler; Siegmar Koeppe; Winfried Kamp; Hans Mulatz; Doris Schmitt-Landsiedel (ISSCC, 2008)

A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion. - Stephan Henzler; Siegmar Koeppe; Dominik Lorenz; Winfried Kamp; Ronald Kuenemund; Doris Schmitt-Landsiedel (IEEE J. Solid State Circuits, 2008)

Design and Application of Power Optimized High-Speed CMOS Frequency Dividers. - Stephan Henzler; Siegmar Koeppe (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Adaptive circuit block model for power supply noise analysis of low power system-on-chip. - Matthias Eireiner; Doris Schmitt-Landsiedel; Paul Wallner; Andreas Schöne; Stephan Henzler; Ulrich Fiedler (SoC, 2009)

Digitalization of mixed-signal functionality in nanometer technologies. - Stephan Henzler (ICCAD, 2010)

A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. - Junjie Kong; Stephan Henzler; Doris Schmitt-Landsiedel; Liter Siek (APCCAS, 2016)