Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor. - Stéphan Jourdan; Pascal Sainrat; Daniel Litaize (ISCA, 1995)

An investigation of the performance of various instruction-issue buffer topologies. - Stéphan Jourdan; Pascal Sainrat; Daniel Litaize (MICRO, 1995)

The effects of mispredicted-path execution on branch prediction structures. - Stéphan Jourdan; Tse-Hao Hsing; Jared Stark; Yale N. Patt (IEEE PACT, 1996)

Multiple-Block Ahead Branch Predictors. - André Seznec; Stéphan Jourdan; Pascal Sainrat; Pierre Michaud (ASPLOS, 1996)

Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution. - Stéphan Jourdan; Jared Stark; Tse-Hao Hsing; Yale N. Patt (Int. J. Parallel Program., 1997)

A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification. - Stéphan Jourdan; Ronny Ronen; Michael Bekerman; Bishara Shomar; Adi Yoaz (MICRO, 1998)

Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors. - Pierre Michaud; André Seznec; Stéphan Jourdan (IEEE PACT, 1999)

Correlated Load-Address Predictors. - Michael Bekerman; Stéphan Jourdan; Ronny Ronen; Gilad Kirshenboim; Lihu Rappoport; Adi Yoaz; Uri C. Weiser (ISCA, 1999)

Speculation Techniques for Improving Load Related Instruction Scheduling. - Adi Yoaz; Mattan Erez; Ronny Ronen; Stéphan Jourdan (ISCA, 1999)

eXtended Block Cache. - Stéphan Jourdan; Lihu Rappoport; Yoav Almog; Mattan Erez; Adi Yoaz; Ronny Ronen (HPCA, 2000)

Early load address resolution via register tracking. - Michael Bekerman; Adi Yoaz; Freddy Gabbay; Stéphan Jourdan; Maxim Kalaev; Ronny Ronen (ISCA, 2000)

An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors. - Pierre Michaud; André Seznec; Stéphan Jourdan (Int. J. Parallel Program., 2001)

A stateless, content-directed data prefetching mechanism. - Robert Cooksey; Stéphan Jourdan; Dirk Grunwald (ASPLOS, 2002)

Transitioning the Intel® next generation microarchitectures (nehalem and westmere) into the mainstream. - Lily Pao Looi; Stéphan Jourdan (Hot Chips Symposium, 2009)

Haswell: The Fourth-Generation Intel Core Processor. - Per Hammarlund; Alberto J. Martinez; Atiq A. Bajwa; David L. Hill; Erik G. Hallnor; Hong Jiang; Martin G. Dixon; Michael Derr; Mikal Hunsaker; Rajesh Kumar; Randy B. Osborne; Ravi Rajwar; et al. (IEEE Micro, 2014)