A model and implementation of a universal time delay simulator for large digital nets. - Stephen A. Szygenda; David M. Rouse; Edward W. Thompson (AFIPS Spring Joint Computing Conference, 1970)

Coding techniques for failure recovery in a distributive modular memory organization. - Stephen A. Szygenda; Michael J. Flynn (AFIPS Spring Joint Computing Conference, 1971)

Time flow mechanisms for use in digital logic simulation. - Stephen A. Szygenda; Cliff W. Hemming Jr.; John M. Hemphill (WSC, 1971)

Modular requirements for digital logic simulation at a predefined functional level. - Cliff W. Hemming Jr.; Stephen A. Szygenda (ACM Annual Conference (1), 1972)

Fault insertion techniques and models for digital logic simulation. - Stephen A. Szygenda; Edward W. Thompson (AFIPS Fall Joint Computing Conference (2), 1972)

TEGAS2 - anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic. - Stephen A. Szygenda (DAC, 1972)

Techniques and modules for element specification in a time - delay logic simulator. - John L. Fike; Stephen A. Szygenda (ANSS, 1973)

Integrated techniques for functional and gate-level digital logic simulation. - Stephen A. Szygenda; Anthony A. Lekkos (DAC, 1973)

Deriving Design Guidelines for Diagnosable Computer Systems. - John M. Hemphill; Stephen A. Szygenda (ISCA, 1973)

Timing analysis for digital fault simulation using assignable delays. - Edward W. Thompson; Stephen A. Szygenda; N. Billawala; R. Pierce (DAC, 1974)

Implemented techniques for handling spikes in an assignable delay simulator. - Stephen A. Szygenda; Anthony A. Lekkos; John L. Fike (WSC, 1974)

Three levels of accuracy for the simulation of different fault types in digital systems. - Edward W. Thompson; Stephen A. Szygenda (DAC, 1975)

Digital Systems Simulation. - Stephen A. Szygenda (Computer, 1975)

Digital Logic Simulation in a Time-Based, Table-Driven Environment. - Edward W. Thompson; Stephen A. Szygenda (Computer, 1975)

A Data Structure and Drive Mechanism for a Table-Driven Simulation System Employing Multilevel Structural Representations of Digital Systems. - N. Billawala; Stephen A. Szygenda; Ewald W. Thomson (ICSE, 1976)

Modeling and Digital Simulation for Design Verification and Diagnosis. - Stephen A. Szygenda; Edward W. Thompson (IEEE Trans. Computers, 1976)

Design of a diagnosable and fault-tolerant input/output controller. - Ajoy K. Bose; Stephen A. Szygenda (AFIPS National Computer Conference, 1977)

Detection of static and dynamic hazards in logic nets. - Ajoy K. Bose; Stephen A. Szygenda (DAC, 1977)

Technology transfer: commercializing university research. - Stephen A. Szygenda; M. Wilson (FJCC, 1987)

SMARTGEN: The Implementation of an Expert System for the Generation of Digital Logic Diagnostic Tests. - Asad Karim; Stephen A. Szygenda (IEA/AIE (Vol. 1), 1988)

MixMOS: a mixed-level simulator for digital MOS circuits using a new algebraic approach. - Jin-Hyeung Kong; Stephen A. Szygenda (Comput. Aided Des., 1990)

The automatic element routine generator: an automatic programming tool for functional simulator design. - Cheng-I Chuang; Stephen A. Szygenda; James D. Baker (Annual Simulation Symposium, 1992)

New design error modeling and metrics for design validation. - Sungho Kang 001; Stephen A. Szygenda (EURO-DAC, 1992)

Modeling and Simulation of Design Errors. - Sungho Kang 001; Stephen A. Szygenda (ICCD, 1992)

Automatic VHDL Model Generation System. - Sungho Kang 001; Stephen A. Szygenda (CHDL, 1993)

m3D: A Multidimensional Dynamic Configurable Router. - Charles Wiley; K. M. Lau; Stephen A. Szygenda (ISCAS, 1993)

Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling. - Sungho Kang 001; Stephen A. Szygenda (IEEE Des. Test Comput., 1994)

Automatic Functional Model Generation for Parallel Fault and Design Error Simulations. - Shuchih Ernest Chang; Stephen A. Szygenda (Int. J. Artif. Intell. Tools, 1994)

Automatic Simulator Generation System. - Sungho Kang 001; Stephen A. Szygenda (Simul., 1994)

The simulation automation system (SAS); concepts, implementation, and results. - Sungho Kang 001; Stephen A. Szygenda (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Special purpose array processor for digital logic simulation. - Youngmin Hur; Stephen A. Szygenda (Annual Simulation Symposium, 1995)

Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation. - Youngmin Hur; Stephen A. Szygenda; E. Scott Fehr; Granville E. Ott; Sungho Kang 001 (HPCA, 1995)

Statistics on concurrent fault and design error simulation. - Brian Grayson; Saghir A. Shaikh; Stephen A. Szygenda (ICCD, 1995)

A Simulation Tool for Design Error Models Utilizing Error Compression and Sampling. - Youngmin Hur; Stephen A. Szygenda (Annual Simulation Symposium, 1996)

A Graphical Simulation and Automatic Model Generation System. - Youngmin Hur; Stephen A. Szygenda (ESM, 1996)

CON2FERS: A Concurrent Concurrent Fault and Design Error Simulator. - Saghir A. Shaikh; Silvian Goldenberg; Stephen A. Szygenda (PDPTA, 1996)

An Integrated Hardware Array for Very High Speed Logic Simulation. - E. Scott Fehr; Stephen A. Szygenda; Granville E. Ott (VLSI Design, 1996)

A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture. - Sungho Kang 001; Youngmin Hur; Stephen A. Szygenda (VLSI Design, 1996)

Concurrent Fault and Design Error Simulation in Interactive Simulation Automation System. - Youngmin Hur; Saghir A. Shaikh; Silvian Goldenberg; Dominik Kacprzak; Stephen A. Szygenda (Annual Simulation Symposium, 1997)

Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation. - Saghir A. Shaikh; Stephen A. Szygenda (Annual Simulation Symposium, 1997)

Multiresolution BSP Trees Applied to Terrain, Transparency, and General Objects. - Charles Wiley; A. T. Campbell III; Stephen A. Szygenda; Donald S. Fussell; Fred Hudson (Graphics Interface, 1997)

Accurate Logic Simulation by Overcoming the Unknown Value Propagation Problem. - Sungho Kang 001; Stephen A. Szygenda (Simul., 2003)

Test vector generation and classification using FSM traversals. - Ralph Marczynski; Mitchell A. Thornton; Stephen A. Szygenda (ISCAS (5), 2004)

A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking. - Lun Li; Mitchell A. Thornton; Stephen A. Szygenda (ISVLSI, 2004)

Components of disaster-tolerant computing: analysis of disaster recovery, IT application downtime and executive visibility. - Chad M. Lawler; Michael A. Harper; Stephen A. Szygenda; Mitchell A. Thornton (Int. J. Bus. Inf. Syst., 2008)

A Systems Engineering Approach for Identifying the Most Critical Links of a Highway System: A Framework Consisting of a Methodology and Mathematical Model. - Gerard Ibarra; Jerrell T. Stracener; Stephen A. Szygenda (IEEE Syst. J., 2008)

System Probability Distribution Modeling Using MDDs. - Mitchell A. Thornton; Theodore W. Manikas; Stephen A. Szygenda; Shinobu Nagayama (ISMVL, 2014)