Double Phase Fault Collapsing with Linear Complexity in Digital Circuits. - Raimund Ubar; Lembit Jurimagi; Elmet Orasson; Galina Josifovska; Stephen Adeboye Oyeniran (DSD, 2015)

Multiple fault testing in systems-on-chip with high-level decision diagrams. - Raimund Ubar; Stephen Adeboye Oyeniran; Mario Schölzel; Heinrich Theodor Vierhaus (IDT, 2015)

Multiple control fault testing in digital systems with high-level decision diagrams. - Raimund Ubar; Stephen Adeboye Oyeniran (AQTR, 2016)

High-level modeling and testing of multiple control faults in digital systems. - Artjom Jasnetski; Stephen Adeboye Oyeniran; Anton Tsertov; Mario Schölzel; Raimund Ubar (DDECS, 2016)

From online fault detection to fault management in Network-on-Chips: A ground-up approach. - Siavoosh Payandeh Azad; Behrad Niazmand; Karl Janson; Nevin George; Stephen Adeboye Oyeniran; Tsotne Putkaradze; Apneet Kaur; Jaan Raik; Gert Jervan; Raimund Ubar; Thomas Hollstein (DDECS, 2017)

High-level test data generation for software-based self-test in microprocessors. - Adeboye Stephen Oyeniran; Artjom Jasnetski; Anton Tsertov; Raimund Ubar (MECO, 2017)

High-level test generation for processing elements in many-core systems. - Stephen Adeboye Oyeniran; Raimund Ubar; Siavoosh Payandeh Azad; Jaan Raik (ReCoSoC, 2017)

Combined pseudo-exhaustive and deterministic testing of array multipliers. - Adeboye Stephen Oyeniran; Siavoosh Payandeh Azad; Raimund Ubar (AQTR, 2018)

Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells. - Siavoosh Payandeh Azad; Adeboye Stephen Oyeniran; Raimund Ubar (DDECS, 2018)

Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation. - Adeboye Stephen Oyeniran; Siavoosh Payandeh Azad; Raimund Ubar (ISCAS, 2018)

New categories of Safe Faults in a processor-based Embedded System. - Cemil Cem Gürsoy; Maksim Jenihhin; Adeboye Stephen Oyeniran; Davide Piumatti; Jaan Raik; Matteo Sonza Reorda; Raimund Ubar (DDECS, 2019)

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Cemil Cem Gürsoy; Jaan Raik (ETS, 2019)

Application Specific True Critical Paths Identification in Sequential Circuits. - Lembit Jürimägi; Raimund Ubar; Maksim Jenihhin; Jaan Raik; Sergei Devadze; Adeboye Stephen Oyeniran (IOLTS, 2019)

Mixed-level identification of fault redundancy in microprocessors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Cemil Cem Gürsoy; Jaan Raik (LATS, 2019)

High-Level Functional Test Generation for Microprocessor Modules. - Adeboye Stephen Oyeniran; Raimund Ubar (MIXDES, 2019)

Implementation-Independent Functional Test Generation for MSC Microprocessors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (VLSI-SoC, 2019)

On Test Generation for Microprocessors for Extended Class of Functional Faults. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (VLSI-SoC (Selected Papers), 2019)

High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Cemil Cem Gürsoy; Jaan Raik (CoRR, 2019)

Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (DSD, 2020)

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (J. Electron. Test., 2020)

Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules. - Maksim Jenihhin; Adeboye Stephen Oyeniran; Jaan Raik; Raimund Ubar (DSD, 2021)

High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test. - Adeboye Stephen Oyeniran; Maksim Jenihhin; Jaan Raik; Raimund Ubar (ISVLSI, 2022)