Flexibility of interconnection structures for field-programmable gate arrays. - Jonathan Rose; Stephen Brown 003 (IEEE J. Solid State Circuits, 1991)

Improving FPGA Routing Architectures Using Architecture and CAD Interactions. - Benjamin Tseng; Jonathan Rose; Stephen Brown 003 (ICCD, 1992)

A detailed router for field-programmable gate arrays. - Stephen Brown 003; Jonathan Rose; Zvonko G. Vranesic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

A stochastic model to predict the routability of field-programmable gate arrays. - Stephen Dean Brown; Jonathan Rose; Zvonko G. Vranesic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. - Stephen Brown 003; Naraig Manjikian; Zvonko G. Vranesic; S. Caranci; A. Grbic; R. Grindley; M. Gusat; K. Loveless; Zeljko Zilic; Sinisa Srbljic (DAC, 1996)

Hybrid FPGA Architecture. - Alireza Kaviani; Stephen Brown 003 (FPGA, 1996)

FPGA Architectural Research: A Survey. - Stephen Brown 003 (IEEE Des. Test Comput., 1996)

Minimizing FPGA Interconnect Delays. - Stephen Brown 003; Muhammad M. Khellah; Zvonko G. Vranesic (IEEE Des. Test Comput., 1996)

FPGA and CPLD Architectures: A Tutorial. - Stephen Brown 003; Jonathan Rose (IEEE Des. Test Comput., 1996)

Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays. - Stephen Brown 003; Muhammad M. Khellah; Guy Lemieux (VLSI Design, 1996)

On two-step routing for FPGAS. - Guy G. Lemieux; Stephen Dean Brown; Daniel Vranesic (ISPD, 1997)

Computational field programmable architecture. - Alireza Kaviani; Daniel Vranesic; Stephen Brown 003 (CICC, 1998)

Technology Mapping for Large Complex PLDs. - Jason Helge Anderson; Stephen Dean Brown (DAC, 1998)

Design and Implementation of the NUMAchine Multiprocessor. - A. Grbic; Stephen Brown 003; S. Caranci; R. Grindley; M. Gusat; Guy G. Lemieux; K. Loveless; Naraig Manjikian; Sinisa Srbljic; Michael Stumm; Zvonko G. Vranesic; Zeljko Zilic (DAC, 1998)

An LPGA with Foldable PLA-style Logic Blocks. - Jason Helge Anderson; Stephen Dean Brown (FPGA, 1998)

The Hybrid Field-Programmable Architecture. - Alireza Kaviani; Stephen Brown 003 (IEEE Des. Test Comput., 1999)

Technology mapping issues for an FPGA with lookup tables and PLA-like blocks. - Alireza Kaviani; Stephen Brown 003 (FPGA, 2000)

The NUMAchine Multiprocessor. - R. Grindley; Tarek S. Abdelrahman; Stephen Brown 003; S. Caranci; D. DeVries; Benjamin Gamsa; A. Grbic; M. Gusat; R. Ho; Orran Krieger; Guy G. Lemieux; K. Loveless; et al. (ICPP, 2000)

The case for registered routing switches in field programmable gate arrays. - Deshanand P. Singh; Stephen Dean Brown (FPGA, 2001)

Integrated retiming and placement for field programmable gate arrays. - Deshanand P. Singh; Stephen Dean Brown (FPGA, 2002)

Constrained clock shifting for field programmable gate arrays. - Deshanand P. Singh; Stephen Dean Brown (FPGA, 2002)

Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. - Valavan Manohararajah; Terry P. Borer; Stephen Dean Brown; Zvonko G. Vranesic (FPL, 2002)

The effect of cluster packing and node duplication control in delay driven clustering. - Mehrdad Eslami Dehkordi; Stephen Dean Brown (FPT, 2002)

Incremental placement for layout driven optimizations on FPGAs. - Deshanand P. Singh; Stephen Dean Brown (ICCAD, 2002)

Recursive circuit clustering for minimum delay and area. - Mehrdad Eslami Dehkordi; Stephen Dean Brown (FPGA, 2003)

Performance-driven recursive multi-level clustering. - Mehrdad Eslami Dehkordi; Stephen Dean Brown (FPT, 2003)

Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. - Deshanand P. Singh; Terry P. Borer; Stephen Dean Brown (VLSI, 2003)

Use of HDLs in teaching of computer hardware courses. - Zvonko G. Vranesic; Stephen Brown 003 (WCAE, 2003)

Retiming aware clustering for sequential circuits. - Mehrdad Eslami Dehkordi; Stephen Dean Brown (FPT, 2004)

The Quartus University Interface Program: enabling advanced FPGA research. - Shawn Malhotra; Terry P. Borer; Deshanand P. Singh; Stephen Dean Brown (FPT, 2004)

Two-stage physical synthesis for FPGAs. - Deshanand P. Singh; Valavan Manohararajah; Stephen Dean Brown (CICC, 2005)

FPGA technology mapping: a study of optimality. - Andrew C. Ling; Deshanand P. Singh; Stephen Dean Brown (DAC, 2005)

Incremental retiming for FPGA physical synthesis. - Deshanand P. Singh; Valavan Manohararajah; Stephen Dean Brown (DAC, 2005)

FPGA PLB Evaluation using Quantified Boolean Satisfiability. - Andrew C. Ling; Deshanand P. Singh; Stephen Dean Brown (FPL, 2005)

Post-Placement BDD-Based Decomposition for FPGAs. - Valavan Manohararajah; Deshanand P. Singh; Stephen Dean Brown (FPL, 2005)

Experiences with Soft-Core Processor Design. - Franjo Plavec; Blair Fort; Zvonko G. Vranesic; Stephen Dean Brown (IPDPS, 2005)

FPGA Logic Synthesis Using Quantified Boolean Satisfiability. - Andrew C. Ling; Deshanand P. Singh; Stephen Dean Brown (SAT, 2005)

A Multithreaded Soft Processor for SoPC Area Reduction. - Blair Fort; Davor Capalija; Zvonko G. Vranesic; Stephen Dean Brown (FCCM, 2006)

Modular Partitioning for Incremental Compilation. - Mehrdad Eslami Dehkordi; Stephen Dean Brown; Terry P. Borer (FPL, 2006)

Adaptive FPGAs: High-Level Architecture and a Synthesis Method. - Valavan Manohararajah; Stephen Dean Brown; Zvonko G. Vranesic (FPL, 2006)

Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. - Gordon R. Chiu; Deshanand P. Singh; Valavan Manohararajah; Stephen Dean Brown (ICCAD, 2006)

Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. - Valavan Manohararajah; Gordon R. Chiu; Deshanand P. Singh; Stephen Dean Brown (SLIP, 2006)

Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. - Valavan Manohararajah; Stephen Dean Brown; Zvonko G. Vranesic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

BddCut: Towards Scalable Symbolic Cut Enumeration. - Andrew C. Ling; Jianwen Zhu; Stephen Dean Brown (ASP-DAC, 2007)

Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. - Tomasz S. Czajkowski; Stephen Dean Brown (DAC, 2007)

On Digital Search Trees - A Simple Method for Constructing Balanced Binary Trees. - Franjo Plavec; Zvonko G. Vranesic; Stephen Brown 003 (ICSOFT (PL/DPS/KE/MUSE), 2007)

Leveraging FPGA Technology for Digital Logic and Embedded Systems Education. - Stephen Brown 003 (MSE, 2007)

Incremental placement for structured ASICs using the transportation problem. - Andrew C. Ling; Deshanand P. Singh; Stephen Dean Brown (VLSI-SoC, 2007)

An area-efficient timing closure technique for FPGAs using Shannon's expansion. - Deshanand P. Singh; Stephen Dean Brown (Integr., 2007)

FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. - Andrew C. Ling; Deshanand P. Singh; Stephen Dean Brown (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. - Valavan Manohararajah; Gordon R. Chiu; Deshanand P. Singh; Stephen Dean Brown (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Towards Compilation of Streaming Programs into FPGA Hardware. - Franjo Plavec; Zvonko G. Vranesic; Stephen Brown 003 (FDL, 2008)

Stream Programming for FPGAs. - Franjo Plavec; Zvonko G. Vranesic; Stephen Brown 003 (FDL (Selected Papers), 2008)

Fast toggle rate computation for FPGA circuits. - Tomasz S. Czajkowski; Stephen Dean Brown (FPL, 2008)

Delay driven AIG restructuring using slack budget management. - Andrew C. Ling; Jianwen Zhu; Stephen Dean Brown (ACM Great Lakes Symposium on VLSI, 2008)

Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs. - Tomasz S. Czajkowski; Stephen Dean Brown (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Scalable Synthesis and Clustering Techniques Using Decision Diagrams. - Andrew C. Ling; Jianwen Zhu; Stephen Dean Brown (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Towards automated ECOs in FPGAs. - Andrew C. Ling; Stephen Dean Brown; Jianwen Zhu; Sean Safarpour (FPGA, 2009)

Enhancements to FPGA design methodology using streaming. - Franjo Plavec; Zvonko G. Vranesic; Stephen Brown 003 (FPL, 2009)

Recent FPGA Advances and Challenges. - Vaughn Betz; Stephen Brown 003 (ERSA, 2010)

Technology issues facing the world's largest integrated circuits. - Stephen Brown 003 (FPT, 2010)

Decomposition-Based Vectorless Toggle Rate Computation for FPGA Circuits. - Tomasz S. Czajkowski; Stephen Dean Brown (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Low-cost hardware profiling of run-time and energy in FPGA embedded processors. - Mark Aldham; Jason Helge Anderson; Stephen Brown 003; Andrew Canis (ASAP, 2011)

LegUp: high-level synthesis for FPGA-based processor/accelerator systems. - Andrew Canis; Jongsok Choi; Mark Aldham; Victor Zhang; Ahmed Kammoona; Jason Helge Anderson; Stephen Brown 003; Tomasz S. Czajkowski (FPGA, 2011)

Toward Automated ECOs in FPGAs. - Andrew C. Ling; Stephen Dean Brown; Sean Safarpour; Jianwen Zhu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems. - Jongsok Choi; Kevin Nam; Andrew Canis; Jason Helge Anderson; Stephen Brown 003; Tomasz S. Czajkowski (FCCM, 2012)

Impact of FPGA architecture on resource sharing in high-level synthesis. - Stefan Hadjis; Andrew Canis; Jason Helge Anderson; Jongsok Choi; Kevin Nam; Stephen Brown 003; Tomasz S. Czajkowski (FPGA, 2012)

From software to accelerators with LegUp high-level synthesis. - Andrew Canis; Jongsok Choi; Blair Fort; Ruolong Lian; Qijing Huang 001; Nazanin Calagar; Marcel Gort; Jia Jun Qin; Mark Aldham; Tomasz S. Czajkowski; Stephen Brown 003; Jason Helge Anderson (CASES, 2013)

Multi-pumping for resource reduction in FPGA high-level synthesis. - Andrew Canis; Jason Helge Anderson; Stephen Dean Brown (DATE, 2013)

The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs. - Qijing Huang 001; Ruolong Lian; Andrew Canis; Jongsok Choi; Ryan Xi; Stephen Brown 003; Jason Helge Anderson (FCCM, 2013)

High-level synthesis with LegUp: a crash course for users and researchers. - Jason Helge Anderson; Stephen Dean Brown; Andrew Canis; Jongsok Choi (FPGA, 2013)

From C to Blokus Duo with LegUp high-level synthesis. - Jiu Cheng Cai; Ruolong Lian; Mengyao Wang; Andrew Canis; Jongsok Choi; Blair Fort; Eric Hart; Emily Miao; Yanyan Zhang; Nazanin Calagar; Stephen Brown 003; Jason Helge Anderson (FPT, 2013)

From software threads to parallel hardware in high-level synthesis for FPGAs. - Jongsok Choi; Stephen Brown 003; Jason Helge Anderson (FPT, 2013)

LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems. - Andrew Canis; Jongsok Choi; Mark Aldham; Victor Zhang; Ahmed Kammoona; Tomasz S. Czajkowski; Stephen Dean Brown; Jason Helge Anderson (ACM Trans. Embed. Comput. Syst., 2013)

Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs. - Franjo Plavec; Zvonko G. Vranesic; Stephen Brown 003 (ACM Trans. Reconfigurable Technol. Syst., 2013)

Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis. - Blair Fort; Andrew Canis; Jongsok Choi; Nazanin Calagar; Ruolong Lian; Stefan Hadjis; Yu Ting Chen; Mathew Hall; Bain Syrowik; Tomasz S. Czajkowski; Stephen Brown 003; Jason Helge Anderson (EUC, 2014)

Source-level debugging for FPGA high-level synthesis. - Nazanin Calagar; Stephen Dean Brown; Jason Helge Anderson (FPL, 2014)

Modulo SDC scheduling with recurrence minimization in high-level synthesis. - Andrew Canis; Stephen Dean Brown; Jason Helge Anderson (FPL, 2014)

Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware. - Jongsok Choi; Stephen Brown 003; Jason Helge Anderson (FPT, 2015)

The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware. - Qijing Huang 001; Ruolong Lian; Andrew Canis; Jongsok Choi; Ryan Xi; Nazanin Calagar; Stephen Brown 003; Jason Helge Anderson (ACM Trans. Reconfigurable Technol. Syst., 2015)

LegUp High-Level Synthesis. - Andrew Canis; Jongsok Choi; Blair Fort; Bain Syrowik; Ruolong Lian; Yu Ting Chen; Hsuan Hsiao; Jeffrey B. Goeders; Stephen Brown 003; Jason Helge Anderson (FPGAs for Software Programmers, 2016)

A unified software approach to specify pipeline and spatial parallelism in FPGA hardware. - Jongsok Choi; Ruolong Lian; Stephen Brown 003; Jason Helge Anderson (ASAP, 2016)

A Survey and Evaluation of FPGA High-Level Synthesis Tools. - Razvan Nane; Vlad Mihai Sima; Christian Pilato; Jongsok Choi; Blair Fort; Andrew Canis; Yu Ting Chen; Hsuan Hsiao; Stephen Brown 003; Fabrizio Ferrandi; Jason Helge Anderson; Koen Bertels (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

FISH: Linux system calls for FPGA accelerators. - Kevin Nam; Blair Fort; Stephen Brown 003 (FPL, 2017)

From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAs. - Jongsok Choi; Stephen Dean Brown; Jason Helge Anderson (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Use of CPU Performance Counters for Accelerator Selection in HLS-Generated CPU-Accelerator Systems. - Bain Syrowik; Blair Fort; Stephen Dean Brown (HEART, 2018)

Using OpenCL to Enable Software-like Development of an FPGA-Accelerated Biophotonic Cancer Treatment Simulator. - Tanner Young-Schultz; Lothar Lilge; Stephen Brown 003; Vaughn Betz (FPGA, 2020)

Leveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array Architectures. - Linqiao Liu; Stephen Brown 003 (FPL, 2021)