A 10-b 20-Msample/s analog-to-digital converter. - Stephen H. Lewis; H. Scott Fetterman; George F. Gross; Ravi Ramachandran; T. R. Viswanathan 001 (IEEE J. Solid State Circuits, 1992)

A median peak detecting analog signal processor for hard disk drive servo. - Krhishnaswamy Nagaraj; Stephen H. Lewis; Robert W. Walden; Glen E. Offord; Reza S. Shariatdoust; Jyoti A. Sabnis; Robert O. Peruzzi; Jeffrey R. Barner; Joseph Plany; Robert P. Mento; Vafa A. Rakshani; Richard W. Hull (IEEE J. Solid State Circuits, 1995)

An 80-Msample/s video switched-capacitor filter using a parallel biquadratic structure. - Steven K. Berg; Paul J. Hurst; Stephen H. Lewis (IEEE J. Solid State Circuits, 1995)

A CMOS continuous-time NTSC-to-color-difference decoder. - James F. Parker; K. Wayne Current; Stephen H. Lewis (IEEE J. Solid State Circuits, 1995)

A 20-Msample/s switched-capacitor finite-impulse-response filter using a transposed structure. - Bret C. Rothenberg; Stephen H. Lewis; Paul J. Hurst (IEEE J. Solid State Circuits, 1995)

A second-order double-sampled delta-sigma modulator using additive-error switching. - Ted Vinko Burmas; Kenneth C. Dyer; Paul J. Hurst; Stephen H. Lewis (IEEE J. Solid State Circuits, 1996)

A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers. - Krishnaswamy Nagaraj; H. Scott Fetterman; Joseph Anidjar; Stephen H. Lewis; Robert G. Renninger (IEEE J. Solid State Circuits, 1997)

A mixed-signal RAM decision-feedback equalizer for disk drives. - Bret C. Rothenberg; James E. C. Brown; Paul J. Hurst; Stephen H. Lewis (IEEE J. Solid State Circuits, 1997)

A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection. - Tanchu Shih; Lawrence Der; Stephen H. Lewis; Paul J. Hurst (IEEE J. Solid State Circuits, 1997)

A second-order double-sampled delta-sigma modulator using individual-level averaging. - Chuc K. Thanh; Stephen H. Lewis; Paul J. Hurst (IEEE J. Solid State Circuits, 1997)

An analog background calibration technique for time-interleaved analog-to-digital converters. - Kenneth C. Dyer; Daihong Fu; Stephen H. Lewis; Paul J. Hurst (IEEE J. Solid State Circuits, 1998)

A digital background calibration technique for time-interleaved analog-to-digital converters. - Daihong Fu; Kenneth C. Dyer; Stephen H. Lewis; Paul J. Hurst (IEEE J. Solid State Circuits, 1998)

A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD. - Ozan E. Erdogan; Paul J. Hurst; Stephen H. Lewis (IEEE J. Solid State Circuits, 1999)

New associate editor [Editor]. - Stephen H. Lewis (IEEE J. Solid State Circuits, 2000)

New associate editor. - Stephen H. Lewis (IEEE J. Solid State Circuits, 2001)

Editorial. - Stephen H. Lewis (IEEE J. Solid State Circuits, 2001)

An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration. - Jun Ming; Stephen H. Lewis (IEEE J. Solid State Circuits, 2001)

A CMOS bandgap reference without resistors. - Arne E. Buck; Charles L. McDonald; Stephen H. Lewis; T. R. Viswanathan 001 (IEEE J. Solid State Circuits, 2002)

A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration. - Shafiq M. Jamal; Daihong Fu; Nick C.-J. Chang; Paul J. Hurst; Stephen H. Lewis (IEEE J. Solid State Circuits, 2002)

A 12-bit 20-MS/s pipelined ADC with nested digital background calibration. - Xiaoyue Wang; Paul J. Hurst; Stephen H. Lewis (CICC, 2003)

Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue. - Eric B. Blecker; Thomas M. McDonald 002; Ozan E. Erdogan; Paul J. Hurst; Stephen H. Lewis (IEEE J. Solid State Circuits, 2003)

A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration. - Xiaoyue Wang; Paul J. Hurst; Stephen H. Lewis (IEEE J. Solid State Circuits, 2004)

Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers. - Paul J. Hurst; Stephen H. Lewis; John P. Keane; Farbod Aram; Kenneth C. Dyer (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter. - Shafiq M. Jamal; Daihong Fu; Mahendra P. Singh; Paul J. Hurst; Stephen H. Lewis (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topology. - Nathaniel J. Guilar; Pak-Kim Lau; Paul J. Hurst; Stephen H. Lewis (CICC, 2005)

Convergence analysis of a background interstage gain calibration technique for pipelined ADCs. - Dong Wang; John P. Keane; Paul J. Hurst; Bernard C. Levy; Stephen H. Lewis (ISCAS (4), 2005)

A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration. - Carl R. Grace; Paul J. Hurst; Stephen H. Lewis (IEEE J. Solid State Circuits, 2005)

Correction to "Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter". - Shafiq M. Jamal; Daihong Fu; Mahendra P. Singh; Paul J. Hurst; Stephen H. Lewis (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Background interstage gain calibration technique for pipelined ADCs. - John P. Keane; Paul J. Hurst; Stephen H. Lewis (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A Unity-Gain Buffer with Reduced Offset and Gain Error. - Guangmao Xing; Stephen H. Lewis; T. R. Viswanathan 001 (CICC, 2006)

Digital background calibration for memory effects in pipelined analog-to-digital converters. - John P. Keane; Paul J. Hurst; Stephen H. Lewis (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Bandwidth Mismatch and Its Correction in Time-Interleaved Analog-to-Digital Converters. - Tsung-Heng Tsai; Paul J. Hurst; Stephen H. Lewis (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A Passive Switched-Capacitor Finite-Impulse-Response Equalizer. - Nathaniel J. Guilar; Frank Lau; Paul J. Hurst; Stephen H. Lewis (IEEE J. Solid State Circuits, 2007)

A 1.4 V Supply CMOS Fractional Bandgap Reference. - Raymond T. Perry; Stephen H. Lewis; A. Paul Brokaw; T. R. Viswanathan 001 (IEEE J. Solid State Circuits, 2007)

An energy-aware multiple-input power supply with charge recovery for energy harvesting applications. - Nathaniel J. Guilar; Rajeevan Amirtharajah; Paul J. Hurst; Stephen H. Lewis (ISSCC, 2009)

Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA. - Haoyue Wang; Xiaoyue Wang; Paul J. Hurst; Stephen H. Lewis (IEEE J. Solid State Circuits, 2009)

Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver. - Tsung-Heng Tsai; Paul J. Hurst; Stephen H. Lewis (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A Level-Crossing Analog-to-Digital Converter With Triangular Dither. - Tunde Wang; Dong Wang; Paul J. Hurst; Bernard C. Levy; Stephen H. Lewis (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Self-Biased Unity-Gain Buffers With Low Gain Error. - Guangmao Xing; Stephen H. Lewis; T. R. Viswanathan 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver. - Mo M. Zhang; Paul J. Hurst; Bernard C. Levy; Stephen H. Lewis (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR. - Kerry A. O'Donoghue; Paul J. Hurst; Stephen H. Lewis (ESSCIRC, 2010)

Calibration of pipelined ADC gain and memory errors in an adaptively equalized receiver. - Mo M. Zhang; Paul J. Hurst; Bernard C. Levy; Stephen H. Lewis (ISCAS, 2010)

Highly programmable switched-capacitor filters using biquads with nonuniform internal clocks. - Oliver E. Gysel; Paul J. Hurst; Stephen H. Lewis (SoCC, 2010)

A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors. - Chi Ho Law; Paul J. Hurst; Stephen H. Lewis (IEEE J. Solid State Circuits, 2010)

Prediction of the Spectrum of a Digital Delta-Sigma Modulator Followed by a Polynomial Nonlinearity. - Kaveh Hosseini; Michael Peter Kennedy; Stephen H. Lewis; Bernard C. Levy (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A Digitally Corrected 5-mW 2-MS/s SC Delta Sigma ADC in 0.25- μ m CMOS With 94-dB SFDR. - Kerry A. O'Donoghue; Paul J. Hurst; Stephen H. Lewis (IEEE J. Solid State Circuits, 2011)

Background adaptive cancellation of digital switching noise in pipelined ADCs without noise sensors. - Nick C.-J. Chang; Paul J. Hurst; Bernard C. Levy; Stephen H. Lewis (CICC, 2012)

A Pipelined ADC With Metastability Error Rate <10-15 Errors/Sample. - Shankar Guhados; Paul J. Hurst; Stephen H. Lewis (IEEE J. Solid State Circuits, 2012)

Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling. - Omar A. Hafiz; Xiaoyue Wang; Paul J. Hurst; Stephen H. Lewis (IEEE J. Solid State Circuits, 2013)

Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without Noise Sensors. - Nick C.-J. Chang; Paul J. Hurst; Bernard C. Levy; Stephen H. Lewis (IEEE J. Solid State Circuits, 2014)

An Integrator-Based Pipelined ADC With Digital Calibration. - Dong Wang; John P. Keane; Paul J. Hurst; Stephen H. Lewis (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

An algorithmic ADC with greater than rail-to-rail input range and near-Vt supply. - Mo M. Zhang; Paul J. Hurst; Stephen H. Lewis (ISCAS, 2016)

Iterative Gain Enhancement in an Algorithmic ADC. - Timothy A. Monk; Paul J. Hurst; Stephen H. Lewis (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Digital Background Calibration of a Split Current-Steering DAC. - David J. Stoops; Jenny Kuo; Paul J. Hurst; Bernard C. Levy; Stephen H. Lewis (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Two-Step ADC With Statistical Calibration. - Yi-Long Yu; Paul J. Hurst; Bernard C. Levy; Stephen H. Lewis (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A Time-Interleaved SAR ADC With Signal-Independent Background Timing Calibration. - Christopher K. Su; Paul J. Hurst; Stephen H. Lewis (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)