WireMap: FPGA technology mapping for improved routability. - Stephen Jang; Billy Chan; Kevin Chung; Alan Mishchenko (FPGA, 2008)

Scalable and scalably-verifiable sequential synthesis. - Alan Mishchenko; Michael L. Case; Robert K. Brayton; Stephen Jang (ICCAD, 2008)

SmartOpt: an industrial strength framework for logic synthesis. - Stephen Jang; Dennis Wu; Mark Jarvin; Billy Chan; Kevin Chung; Alan Mishchenko; Robert K. Brayton (FPGA, 2009)

WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging. - Stephen Jang; Billy Chan; Kevin Chung; Alan Mishchenko (ACM Trans. Reconfigurable Technol. Syst., 2009)

Global delay optimization using structural choices. - Alan Mishchenko; Robert K. Brayton; Stephen Jang (FPGA, 2010)

Delay optimization using SOP balancing. - Alan Mishchenko; Robert K. Brayton; Stephen Jang; Victor N. Kravets (ICCAD, 2011)

Scalable don't-care-based logic optimization and resynthesis. - Alan Mishchenko; Robert K. Brayton; Jie-Hong R. Jiang; Stephen Jang (ACM Trans. Reconfigurable Technol. Syst., 2011)

Mapping into LUT structures. - Sayak Ray; Alan Mishchenko; Niklas Eén; Robert K. Brayton; Stephen Jang; Chao Chen (DATE, 2012)