The P1149.4 Mixed Signal Test Bus: Costs and Benefits. - Stephen K. Sunter (ITC, 1995)

A low cost 100 MHz analog test bus. - Stephen K. Sunter (VTS, 1995)

Design for testability of integrated operational amplifiers using oscillation-test strategy. - Karim Arabi; Bozena Kaminska; Stephen K. Sunter (ICCD, 1996)

P1149.4-Problem or Solution for Mixed-Signal IC Design? - Stephen K. Sunter (ITC, 1997)

A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST. - Stephen K. Sunter; Naveena Nagi (ITC, 1997)

BIST vs. ATE: need a different vehicle? - Stephen K. Sunter (ITC, 1998)

BIST for phase-locked loops in digital applications. - Stephen K. Sunter; Aubin Roy (ITC, 1999)

Test Metrics for Analog Parametric Faults. - Stephen K. Sunter; Naveena Nagi (VTS, 1999)

Analog, digital, and mixed-signal people. - Stephen K. Sunter (IEEE Des. Test Comput., 1999)

How Should Fault Coverage Be Defined? - Thomas W. Williams; Stephen K. Sunter (VTS, 2000)

A general purpose 1149.4 IC with HF analog test capabilities. - Stephen K. Sunter; Ken Filliter; Joe Woo; Pat McHugh (ITC, 2001)

Contactless digital testing of IC pin leakage currents. - Stephen K. Sunter; Charles McDonald; Givargis Danialy 001 (ITC, 2001)

High Accuracy Stimulus Generation for A/D Converter BIST. - Aubin Roy; Stephen K. Sunter; Alessandra Fudoli; Davide Appello (ITC, 2002)

IC Mixed-Signal BIST: Separating Facts from Fiction. - Stephen K. Sunter (ITC, 2002)

Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost. - Stephen K. Sunter; Benoit Nadeau-Dostie (ITC, 2002)

Testing High Frequency ADCs and DACs with a Low Frequency Analog Bus. - Stephen K. Sunter (ITC, 2003)

Status of IEEE Testability Standards 1149.4, 1532 and 1149.6. - Stephen K. Sunter; Adam Osseiran; Adam Cron; Neil G. Jacobson; Dave Bonnett; Bill Eklow; Carl Barnhart; Ben Bennetts (DATE, 2004)

An Automated, Complete, Structural Test Solution for SERDES. - Stephen K. Sunter; Aubin Roy; Jean-Francois Cote (ITC, 2004)

On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz. - Stephen K. Sunter; Aubin Roy (IEEE Des. Test Comput., 2004)

Correct by construction is guaranteed to fail. - Stephen K. Sunter (ITC, 2005)

Structural tests for jitter tolerance in SerDes receivers. - Stephen K. Sunter; Aubin Roy (ITC, 2005)

Analog and mixed signal test techniques for SOC development. - Bozena Kaminska; Stephen K. Sunter; Salvador Mir (Microelectron. J., 2005)

Testing SerDes beyond 4 Gbps - changing priorities. - Stephen K. Sunter; Aubin Roy (CICC, 2007)

Purely Digital BIST for Any PLL or DLL. - Stephen K. Sunter; Aubin Roy (ETS, 2007)

A selt-testing BOST for high-frequency PLLs, DLLs, and SerDes. - Stephen K. Sunter; Aubin Roy (ITC, 2007)

Noise-Insensitive Digital BIST for any PLL or DLL. - Stephen K. Sunter; Aubin Roy (J. Electron. Test., 2008)

Testing bridges to nowhere - combining Boundary Scan and capacitive sensing. - Steve Sunter; Kenneth P. Parker (ITC, 2009)

A Configurable RDF Editor for Australian Curriculum. - Diny Golder; Les Kneebone; Jon Phipps; Steve Sunter; Stuart A. Sutton (ICADL, 2010)

Experiences with parametric BIST for production testing PLLs with picosecond precision. - Rakesh Kinger; Swetha Narasimhawsamy; Stephen K. Sunter (ITC, 2010)

BIST of I/O circuit parameters via standard boundary scan. - Stephen K. Sunter; Matthias Tilmann (ITC, 2010)

A Mixed-Signal Test Bus and Analog BIST with 'Unlimited' Time and Voltage Resolution. - Stephen K. Sunter; Aubin Roy (ETS, 2011)

Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan. - Stephen K. Sunter; Aubin Roy (ITC, 2011)

Small delay testing for TSVs in 3-D ICs. - Shi-Yu Huang; Yu-Hsiang Lin; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter; Yung-Fa Chou; Ding-Ming Kwai (DAC, 2012)

A unified method for parametric fault characterization of post-bond TSVs. - Yu-Hsiang Lin; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter (ITC, 2012)

Contactless Test of IC Pads, Pins, and TSVs via Standard Boundary Scan. - Stephen K. Sunter; Aubin Roy (IEEE Des. Test Comput., 2012)

Mid-bond Interposer Wire Test. - Li-Ren Huang; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter (Asian Test Symposium, 2013)

Oscillation-Based Prebond TSV Test. - Li-Ren Huang; Shi-Yu Huang; Stephen K. Sunter; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. - Yu-Hsiang Lin; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter; Yung-Fa Chou; Ding-Ming Kwai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Innovative practices session 4C: Disruptive solutions in the non-digital world. - Amitava Majumdar 002; Suriya Natarajan; Stephen K. Sunter; Prashant Goteti; Ke Huang 001 (VTS, 2014)

Innovative practices session 7C: Reduced pin-count testing - How low can we go? - Stephen K. Sunter; Steve Comen; Paul Berndt; Ram Rajamani (VTS, 2014)

Streaming fast access to ADCs and DACs for mixed-signal ATPG. - Stephen K. Sunter; Jean-Francois Cote; Jeff Rearick (ITC, 2015)

Streaming Access to ADCs and DACs for Mixed-Signal ATPG. - Stephen K. Sunter; Jean-Francois Cote; Jeff Rearick (IEEE Des. Test, 2016)