Detectable CMOS Faults in Switch-Level Simulation. - Stephen L. Lusky; Thirumalai Sridhar (ITC, 1985)

Synthesis of delay fault testable combinational logic. - Kaushik Roy 001; Jacob A. Abraham; Kaushik De; Stephen L. Lusky (ICCAD, 1989)

A comprehensive delay model for CMOS inverters. - Santanu Dutta; Shivaling S. Mahant-Shetti; Stephen L. Lusky (IEEE J. Solid State Circuits, 1995)