Reprogrammable Platforms for High-Speed Data Acquisition. - Jozsef Ludvig; James G. McCarthy; Stephen Neuendorffer; Sonia R. Sachs (Des. Autom. Embed. Syst., 2002)

Actor-Oriented Design of Embedded Hardware and Software Systems. - Edward A. Lee; Stephen Neuendorffer; Michael J. Wirthlin (J. Circuits Syst. Comput., 2003)

Taming heterogeneity - the Ptolemy approach. - Johan Eker; Jörn W. Janneck; Edward A. Lee; Jie Liu 001; Xiaojun Liu 001; Jozsef Ludvig; Stephen Neuendorffer; Sonia R. Sachs; Yuhong Xiong (Proc. IEEE, 2003)

Classes and subclasses in actor-oriented design. - Edward A. Lee; Stephen Neuendorffer (MEMOCODE, 2004)

Hierarchical reconfiguration of dataflow models. - Stephen Neuendorffer; Edward A. Lee (MEMOCODE, 2004)

Modeling Real-World Control Systems: Beyond Hybrid Systems. - Stephen Neuendorffer (WSC, 2004)

Combining module selection and resource sharing for efficient FPGA pipeline synthesis. - Welson Sun; Michael J. Wirthlin; Stephen Neuendorffer (FPGA, 2006)

FPGA Pipeline Synthesis Design Exploration Using Module Selection and Resource Sharing. - Welson Sun; Michael J. Wirthlin; Stephen Neuendorffer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Streaming Systems in FPGAs. - Stephen Neuendorffer; Kees A. Vissers (SAMOS, 2008)

Using C-to-gates to program streaming image processing kernels efficiently on FPGAs. - Kristof Denolf; Stephen Neuendorffer; Kees A. Vissers (FPL, 2009)

Classes and inheritance in actor-oriented design. - Edward A. Lee; Xiaojun Liu 001; Stephen Neuendorffer (ACM Trans. Embed. Comput. Syst., 2009)

Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools. - Kees A. Vissers; Stephen Neuendorffer; Juanjo Noguera (DATE, 2011)

High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only). - Sven van Haastregt; Stephen Neuendorffer; Kees A. Vissers; Bart Kienhuis (FPGA, 2011)

High-Level Synthesis for FPGAs: From Prototyping to Deployment. - Jason Cong; Bin Liu 006; Stephen Neuendorffer; Juanjo Noguera; Kees A. Vissers; Zhiru Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Building zynq® accelerators with Vivado® high level synthesis. - Stephen Neuendorffer; Fernando Martinez-Vallina (FPGA, 2013)

Parallel Programming for FPGAs. - Ryan Kastner; Janarbek Matai; Stephen Neuendorffer (CoRR, 2018)

Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine. - Prasanth Chatarasi; Stephen Neuendorffer; Samuel Bayliss; Kees A. Vissers; Vivek Sarkar (HPEC, 2020)

ScaleHLS: Scalable High-Level Synthesis through MLIR. - Hanchen Ye; Cong Hao; Jianyi Cheng; Hyunmin Jeong; Jack Huang; Stephen Neuendorffer; Deming Chen (CoRR, 2021)

ScaleHLS: a scalable high-level synthesis framework with multi-level transformations and optimizations: invited. - Hanchen Ye; HyeGang Jun; Hyunmin Jeong; Stephen Neuendorffer; Deming Chen (DAC, 2022)

Compiler-Driven Simulation of Reconfigurable Hardware Accelerators. - Zhijing Li 002; Yuwei Ye; Stephen Neuendorffer; Adrian Sampson (HPCA, 2022)

ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation. - Hanchen Ye; Cong Hao; Jianyi Cheng; Hyunmin Jeong; Jack Huang; Stephen Neuendorffer; Deming Chen (HPCA, 2022)

FPGA HLS Today: Successes, Challenges, and Opportunities. - Jason Cong; Jason Lau; Gai Liu; Stephen Neuendorffer; Peichen Pan; Kees A. Vissers; Zhiru Zhang (ACM Trans. Reconfigurable Technol. Syst., 2022)

Introduction to Special Issue on FPGAs in Data Centers. - Ken Eguro; Stephen Neuendorffer; Viktor K. Prasanna; Hongbo Rong (ACM Trans. Reconfigurable Technol. Syst., 2022)

Introduction to Special Issue on FPGAs in Data Centers, Part II. - Ken Eguro; Stephen Neuendorffer; Viktor K. Prasanna; Hongbo Rong (ACM Trans. Reconfigurable Technol. Syst., 2022)

CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture. - Jinming Zhuang; Jason Lau; Hanchen Ye; Zhuoping Yang; Yubo Du; Jack Lo; Kristof Denolf; Stephen Neuendorffer; Alex K. Jones; Jingtong Hu; Deming Chen; Jason Cong; et al. (FPGA, 2023)

SPADES: A Productive Design Flow for Versal Programmable Logic. - Tan Nguyen; Zachary Blair; Stephen Neuendorffer; John Wawrzynek (FPL, 2023)

Special Issue: "AI Acceleration on FPGAs". - Yun Liang 001; Wei Zhang 012; Stephen Neuendorffer; Wayne Luk (ACM Trans. Embed. Comput. Syst., 2023)

An End-to-End Programming Model for AI Engine Architectures. - Maksim Levental; Arham Khan; Ryan Chard; Kyle Chard; Stephen Neuendorffer; Ian T. Foster (HEART, 2024)

CHARM 2.0: Composing Heterogeneous Accelerators for Deep Learning on Versal ACAP Architecture. - Jinming Zhuang; Jason Lau; Hanchen Ye; Zhuoping Yang; Shixin Ji; Jack Lo; Kristof Denolf; Stephen Neuendorffer; Alex K. Jones; Jingtong Hu; Yiyu Shi 001; Deming Chen; et al. (ACM Trans. Reconfigurable Technol. Syst., 2024)

Efficiency, Expressivity, and Extensibility in a Close-to-Metal NPU Programming Interface. - Erika Hunhoff; Joseph Melber; Kristof Denolf; Andra Bisca; Samuel Bayliss; Stephen Neuendorffer; Jeff Fifield; Jack Lo; Pranathi Vasireddy; Phil James-Roxby; Eric Keller (FCCM, 2025)

IRFuzzer: Specialized Fuzzing for LLVM Backend Code Generation. - Yuyang Rong; Zhanghan Yu; Zhenkai Weng; Stephen Neuendorffer; Hao Chen (ICSE, 2025)