An investigation into the design of high-performance shared buffer architectures based on FPGA technology with embedded memory. - Stephen O'Kane; Sakir Sezer (FPT, 2004)

Implementing High Speed IP Address Lookups in Hardware. - Kieran McLaughlin; Stephen O'Kane; Sakir Sezer (AICT/SAPIR/ELETE, 2005)

The Design and Implementation of a Shared Packet Buffer Architecture for Fixed and Variable Sized Packets. - Stephen O'Kane; Colm McKillen; Sakir Sezer (AICT/SAPIR/ELETE, 2005)

Design and implementation of a shared buffer architecture for a gigabit Ethernet packet switch. - Stephen O'Kane; Sakir Sezer; Ciaran Toal (SoCC, 2005)

A Study of Shared Buffer Memory Segmentation for Packet Switched Networks. - Stephen O'Kane; Sakir Sezer; Lum Soong Lit (AICT/ICIW, 2006)

An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing. - Ciaran Toal; Dwayne Burns; Kieran McLaughlin; Sakir Sezer; Stephen O'Kane (AHS, 2007)