A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces. - Terry I. Chappell; Stanley E. Schuster; Barbara A. Chappell; James W. Allan; Jack Y.-C. Sun; Stephen P. Klepner; Robert L. Franch; Paul F. Greier; Phillip J. Restle (IEEE J. Solid State Circuits, 1989)

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture. - Terry I. Chappell; Barbara A. Chappell; Stanley E. Schuster; James W. Allan; Stephen P. Klepner; Rajiv V. Joshi; Robert L. Franch (IEEE J. Solid State Circuits, 1991)