A self-reconfiguration scheme for fault-tolerant VLSI processor arrays. - Stephen Pateras; Janusz Rajski (ICCD, 1988)

Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits. - Stephen Pateras; Janusz Rajski (DAC, 1991)

Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits. - Stephen Pateras; Janusz Rajski (ITC, 1991)

Avoiding Unknown States When Scanning Mutually Exclusive Latches. - Stephen Pateras; Martin S. Schmookler (ITC, 1995)

Advanced microprocessor test strategy and methodology. - William V. Huott; Timothy J. Koprowski; Bryan J. Robbins; Mary P. Kusko; Stephen Pateras; Dale E. Hoffman; Timothy G. McNamara; Thomas J. Snethen (IBM J. Res. Dev., 1997)

An embedded technique for at-speed interconnect testing. - Benoit Nadeau-Dostie; Jean-Francois Cote; Harry Hulvershorn; Stephen Pateras (ITC, 1999)

Bridging the gap between embedded test and ATE. - Martin Bell; Givargis Danialy 001; Michael C. Howells; Stephen Pateras (ITC, 2000)

Embedded Diagnosis IP. - Stephen Pateras (DATE, 2002)

IP for Embedded Diagnosis. - Stephen Pateras (IEEE Des. Test Comput., 2002)

Achieving At-Speed Structural Test. - Stephen Pateras (IEEE Des. Test Comput., 2003)

Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having Both. - Stephen Pateras (ITC, 2004)