Code Optimization Across Procedures. - Stephen Richardson; Mahadevan Ganapathi (Computer, 1989)

Interprocedural analysis vs. procedure integration. - Stephen Richardson; Mahadevan Ganapathi (Inf. Process. Lett., 1989)

Interprocedural Optimization: Experimental Results. - Stephen Richardson; Mahadevan Ganapathi (Softw. Pract. Exp., 1989)

The Experience of Developing a Large-Scale Natural Language Processing System: Critique. - Stephen Richardson; Lisa C. Braden-Harder (Natural Language Processing, 1993)

Verification of chip multiprocessor memory systems using a relaxed scoreboard. - Ofer Shacham; Megan Wachs; Alex Solomatnikov; Amin Firoozshahian; Stephen Richardson; Mark Horowitz (MICRO, 2008)

A memory system design framework: creating smart memories. - Amin Firoozshahian; Alex Solomatnikov; Ofer Shacham; Zain Asgar; Stephen Richardson; Christos Kozyrakis; Mark Horowitz (ISCA, 2009)

Using a configurable processor generator for computer architecture prototyping. - Alex Solomatnikov; Amin Firoozshahian; Ofer Shacham; Zain Asgar; Megan Wachs; Wajahat Qadeer; Stephen Richardson; Mark Horowitz (MICRO, 2009)

Understanding sources of inefficiency in general-purpose chips. - Rehan Hameed; Wajahat Qadeer; Megan Wachs; Omid Azizi; Alex Solomatnikov; Benjamin C. Lee; Stephen Richardson; Christos Kozyrakis; Mark Horowitz (ISCA, 2010)

Rethinking Digital Design: Why Design Must Change. - Ofer Shacham; Omid Azizi; Megan Wachs; Stephen Richardson; Mark Horowitz (IEEE Micro, 2010)

Intermediate representations for controllers in chip generators. - Kyle Kelley; Megan Wachs; Andrew Danowitz; P. Stevenson; Stephen Richardson; Mark Horowitz (DATE, 2011)

Understanding sources of ineffciency in general-purpose chips. - Rehan Hameed; Wajahat Qadeer; Megan Wachs; Omid Azizi; Alex Solomatnikov; Benjamin C. Lee; Stephen Richardson; Christos Kozyrakis; Mark Horowitz (Commun. ACM, 2011)

Removing overhead from high-level interfaces. - Kyle Kelley; Megan Wachs; John P. Stevenson; Stephen Richardson; Mark Horowitz (DAC, 2012)

Avoiding game over: bringing design to the next level. - Ofer Shacham; Sameh Galal; Sabarish Sankaranarayanan; Megan Wachs; John S. Brunhaver; Artem Vassiliev; Mark Horowitz; Andrew Danowitz; Wajahat Qadeer; Stephen Richardson (DAC, 2012)

Bringing up a chip on the cheap. - Megan Wachs; Ofer Shacham; Zain Asgar; Amin Firoozshahian; Stephen Richardson; Mark Horowitz (IEEE Des. Test, 2012)

An area-efficient minimum-time FFT schedule using single-ported memory. - Stephen Richardson; Ofer Shacham; Dejan Markovic; Mark Horowitz (VLSI-SoC, 2013)

Building Conflict-Free FFT Schedules. - Stephen Richardson; Dejan Markovic; Andrew Danowitz; John S. Brunhaver; Mark Horowitz (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Improving energy efficiency of DRAM by exploiting half page row access. - Heonjae Ha; Ardavan Pedram; Stephen Richardson; Shahar Kvatinsky; Mark Horowitz (MICRO, 2016)

Evaluating programmable architectures for imaging and vision applications. - Artem Vasilyev; Nikhil Bhagdikar; Ardavan Pedram; Stephen Richardson; Shahar Kvatinsky; Mark Horowitz (MICRO, 2016)

A Systematic Approach to Blocking Convolutional Neural Networks. - Xuan Yang; Jing Pu; Blaine Burton Rister; Nikhil Bhagdikar; Stephen Richardson; Shahar Kvatinsky; Jonathan Ragan-Kelley; Ardavan Pedram; Mark Horowitz (CoRR, 2016)

Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. - Ardavan Pedram; Stephen Richardson; Mark Horowitz; Sameh Galal; Shahar Kvatinsky (IEEE Des. Test, 2017)

Programming Heterogeneous Systems from an Image Processing DSL. - Jing Pu; Steven Bell; Xuan Yang; Jeff Setter; Stephen Richardson; Jonathan Ragan-Kelley; Mark Horowitz (ACM Trans. Archit. Code Optim., 2017)

Creating an Agile Hardware Design Flow. - Rick Bahr; Clark W. Barrett; Nikhil Bhagdikar; Alex Carsello; Ross Daly; Caleb Donovick; David Durst; Kayvon Fatahalian; Kathleen Feng; Pat Hanrahan; Teguh Hofstee; Mark Horowitz; et al. (DAC, 2020)

A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs. - Ankita Nayak; Keyi Zhang; Rajsekhar Setaluri; Alex Carsello; Makai Mann; Stephen Richardson; Rick Bahr; Pat Hanrahan; Mark Horowitz; Priyanka Raina (DATE, 2020)

Visualizing Tacit Knowledge in Cardiac Operating Room: A Need-Finding Study. - Soojin Kang; Cecilia Xi Wang; Tjorvi Perry; Stephen Richardson; Lisa Miller (HCI (21), 2022)

Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration. - Kathleen Feng; Alex Carsello; Taeyoung Kong; Kalhan Koul; Qiaoyi Liu; Jackson Melchert; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (HCS, 2022)

Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. - Alex Carsello; Kathleen Feng; Taeyoung Kong; Kalhan Koul; Qiaoyi Liu; Jackson Melchert; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (VLSI Technology and Circuits, 2022)

AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers. - Kalhan Koul; Jackson Melchert; Kavya Sreedhar; Leonard Truong; Gedeon Nyengele; Keyi Zhang; Qiaoyi Liu; Jeff Setter; Po-Han Chen; Yuchen Mei; Maxwell Strange; Ross Daly; et al. (ACM Trans. Embed. Comput. Syst., 2023)

Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains. - Ankita Nayak; Keyi Zhang; Rajsekhar Setaluri; Alex Carsello; Makai Mann; Christopher Torng; Stephen Richardson; Rick Bahr; Pat Hanrahan; Mark Horowitz; Priyanka Raina (ACM Trans. Reconfigurable Technol. Syst., 2023)

Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. - Kathleen Feng; Taeyoung Kong; Kalhan Koul; Jackson Melchert; Alex Carsello; Qiaoyi Liu; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (IEEE J. Solid State Circuits, 2024)