A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. - John E. Barth Jr.; Darren Anand; Steve Burns 001; Jeffrey H. Dreibelbis; John A. Fifield; Kevin W. Gorman; Michael R. Nelms; Erik Nelson; Adrian Paparelli; Gary Pomichter; Dale E. Pontius; Stephen Sliva (IEEE J. Solid State Circuits, 2005)

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. - Darren Anand; Jim Covino; Jeffrey H. Dreibelbis; John A. Fifield; Kevin W. Gorman; Mark Jacunski; Jake Paparelli; Gary Pomichter; Dale E. Pontius; Michael Roberge; Stephen Sliva (CICC, 2007)

Advancements in at-speed array BIST: multiple improvements. - Kevin W. Gorman; Michael Roberge; Adrian Paparelli; Gary Pomichter; Stephen Sliva; William Corbin (ITC, 2007)

A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns. - Mark Jacunski; Darren Anand; Robert Busch; John A. Fifield; Matthew Lanahan; Paul Lane; Adrian Paparelli; Gary Pomichter; Dale E. Pontius; Michael Roberge; Stephen Sliva (CICC, 2010)