Buffer Insertion with Accurate Gate and Interconnect Delay Computation. - Charles J. Alpert; Anirudh Devgan; Stephen T. Quay (DAC, 1999)

Is wire tapering worthwhile? - Charles J. Alpert; Anirudh Devgan; Stephen T. Quay (ICCAD, 1999)

Buffer insertion for noise and delay optimization. - Charles J. Alpert; Anirudh Devgan; Stephen T. Quay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Buffer Library Selection. - José Luis Neves; Stephen T. Quay (ICCD, 2000)

Buffered Steiner trees for difficult instances. - Charles J. Alpert; Milos Hrkic; Jiang Hu; Andrew B. Kahng; John Lillis; Bao Liu 001; Stephen T. Quay; Sachin S. Sapatnekar; A. J. Sullivan; Paul Villarrubia (ISPD, 2001)

Interconnect synthesis without wire tapering. - Charles J. Alpert; Anirudh Devgan; John P. Fishburn; Stephen T. Quay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Steiner tree optimization for buffers, blockages, and bays. - Charles J. Alpert; Gopal Gandham; Jiang Hu; José Luis Neves; Stephen T. Quay; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Correction to "interconnect synthesis without wire tapering". - Charles J. Alpert; Anirudh Devgan; John P. Fishburn; Stephen T. Quay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Porosity aware buffered steiner tree construction. - Charles J. Alpert; Gopal Gandham; Milos Hrkic; Jiang Hu; Stephen T. Quay (ISPD, 2003)

Buffer insertion with adaptive blockage avoidance. - Jiang Hu; Charles J. Alpert; Stephen T. Quay; Gopal Gandham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Fast and flexible buffer trees that navigate the physical layout environment. - Charles J. Alpert; Milos Hrkic; Jiang Hu; Stephen T. Quay (DAC, 2004)

A fast algorithm for identifying good buffer insertion candidate locations. - Charles J. Alpert; Milos Hrkic; Stephen T. Quay (ISPD, 2004)

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. - Charles J. Alpert; Chris C. N. Chu; Gopal Gandham; Milos Hrkic; Jiang Hu; Chandramouli V. Kashyap; Stephen T. Quay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Porosity-aware buffered Steiner tree construction. - Charles J. Alpert; Gopal Gandham; Milos Hrkic; Jiang Hu; Stephen T. Quay; Cliff C. N. Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Fast Electrical Correction Using Resizing and Buffering. - Shrirang K. Karandikar; Charles J. Alpert; Mehmet Can Yildiz; Paul Villarrubia; Stephen T. Quay; T. Mahmud (ASP-DAC, 2007)

Probabilistic Congestion Prediction with Partial Blockages. - Zhuo Li 001; Charles J. Alpert; Stephen T. Quay; Sachin S. Sapatnekar; Weiping Shi (ISQED, 2007)

The nuts and bolts of physical synthesis. - Charles J. Alpert; Shrirang K. Karandikar; Zhuo Li 001; Gi-Joon Nam; Stephen T. Quay; Haoxing Ren; Cliff C. N. Sze; Paul G. Villarrubia; Mehmet Can Yildiz (SLIP, 2007)

Techniques for Fast Physical Synthesis. - Charles J. Alpert; Shrirang K. Karandikar; Zhuo Li 001; Gi-Joon Nam; Stephen T. Quay; Haoxing Ren; Cliff C. N. Sze; Paul G. Villarrubia; Mehmet Can Yildiz (Proc. IEEE, 2007)

Fast interconnect synthesis with layer assignment. - Zhuo Li 001; Charles J. Alpert; Shiyan Hu 001; Tuhin Muhmud; Stephen T. Quay; Paul G. Villarrubia (ISPD, 2008)

Interconnect Optimization Considering Multiple Critical Paths. - Jiang Hu; Ying Zhou; Yaoguang Wei; Stephen T. Quay; Lakshmi N. Reddy; Gustavo E. Téllez; Gi-Joon Nam (ISPD, 2018)