A continuous density neural tree network word spotting system. - Stephen V. Kosonocky; Richard J. Mammone (ICASSP, 1995)

An eight-issue tree-VLIW processor for dynamic binary translation. - Kemal Ebcioglu; Jason Fritts; Stephen Kosonocky; Michael Gschwind; Erik R. Altman; Krishnan Kailas; Terry Bright (ICCD, 1998)

Designing a Testable System on a Chip. - Stephen V. Kosonocky; Arthur A. Bright; Kevin W. Warren; Ruud A. Haring; Steve Klepner; Sameh W. Asaad; S. Basavaiah; Bob Havreluk; David F. Heidel; Michael Immediato; Keith A. Jenkins; Rajiv V. Joshi; et al. (VTS, 1998)

Interconnect-centric Array Architectures for Minimum SRAM Access Time. - Azeez J. Bhavnagarwala; Stephen V. Kosonocky; James D. Meindl (ICCD, 2001)

Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. - W. Chen; Wei Hwang; Prabhakar Kudva; George Gristede; Stephen V. Kosonocky; Rajiv V. Joshi (ISLPED, 2001)

Enchanced multi-threshold (MTCMOS) circuits using variable well bias. - Stephen V. Kosonocky; Michael Immediato; Peter E. Cottrell; Terence B. Hook; Randy W. Mann; Jeff Brown (ISLPED, 2001)

Low power integrated scan-retention mechanism. - Victor V. Zyuban; Stephen V. Kosonocky (ISLPED, 2002)

Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits. - Alice Wang; Anantha P. Chandrakasan; Stephen V. Kosonocky (ISVLSI, 2002)

Minimizing inductive noise in system-on-a-chip with multiple power gating structures. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel; Kevin Stawiasz; David F. Heidel; Michael Immediato (ESSCIRC, 2003)

Understanding and minimizing ground bounce during mode transition of power gating structures. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel (ISLPED, 2003)

Low-power circuits and technology for wireless digital systems. - Stephen V. Kosonocky; Azeez J. Bhavnagarwala; Kenneth Chin; George Gristede; Anne-Marie Haen; Wei Hwang; Mark B. Ketchen; Suhwan Kim 001; Daniel R. Knebel; Kevin W. Warren; Victor V. Zyuban (IBM J. Res. Dev., 2003)

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits. - Jean-Olivier Plouchart; Noah Zamdmer; Jonghae Kim; Melanie Sherony; Yue Tan; Asit Ray; Mohamed Talbi; Lawrence F. Wagner; Kun Wu; Naftali E. Lustig; Shreesh Narasimha; Patricia O'Neil; et al. (IBM J. Res. Dev., 2003)

Characterization of logic circuit techniques for high leakage CMOS technologies. - Phillip Chin; Charles A. Zukowski; George Gristede; Stephen V. Kosonocky (ACM Great Lakes Symposium on VLSI, 2004)

Experimental measurement of a novel power gating structure with intermediate power saving mode. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel; Kevin Stawiasz (ISLPED, 2004)

A synchronous interface for SoCs with multiple clock domains. - Visvesh S. Sathe 001; Conrad H. Ziesler; Marios C. Papaefthymiou; Suhwan Kim 001; Stephen V. Kosonocky (SoCC, 2004)

Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies. - Phillip Chin; Charles A. Zukowski; George Gristede; Stephen V. Kosonocky (Integr., 2005)

Early Power-Aware Design & Validation: Myth or Reality? - Gila Kamhi; Sarah Miller; Stephen Bailey Mentor; Wolfgang Nebel; Y. C. Wong; Juergen Karmann; Enrico Macii; Stephen V. Kosonocky; Steve Curtis (DAC, 2007)

Structured and tuned array generation (STAG) for high-performance random logic. - Matthew M. Ziegler; Gary S. Ditlow; Stephen V. Kosonocky; Zhenyu Qi 001; Mircea R. Stan (ACM Great Lakes Symposium on VLSI, 2007)

Multi-Dimensional Circuit and Micro-Architecture Level Optimization. - Zhenyu Qi 001; Matthew M. Ziegler; Stephen V. Kosonocky; Jan M. Rabaey; Mircea R. Stan (ISQED, 2007)

Introduction to the Special Issue on the 2006 Symposium on VLSI Circuits. - Stephen V. Kosonocky; Kazuo Yano (IEEE J. Solid State Circuits, 2007)

A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel; Kevin Stawiasz; Marios C. Papaefthymiou (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Keeping hot chips cool: are IC thermal problems hot air? - Ruchir Puri; Devadas Varma; Darvin Edwards; Alan J. Weger; Paul D. Franzon; Andrew Yang; Stephen V. Kosonocky (DAC, 2008)

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing. - Azeez J. Bhavnagarwala; Stephen Kosonocky; Carl Radens; Yuen H. Chan; Kevin Stawiasz; Uma Srinivasan 002; Steven P. Kowalczyk; Matthew M. Ziegler (IEEE J. Solid State Circuits, 2008)

An x86-64 core implemented in 32nm SOI CMOS. - Ravi Jotwani; Sriram Sundaram; Stephen Kosonocky; Alex Schaefer; Victor Andrade; Greg Constant; Amy Novak; Sam Naffziger (ISSCC, 2010)

Are you having fun yet? - Stephen V. Kosonocky (IEEE Des. Test Comput., 2010)

Practical power gating and dynamic voltage/frequency scaling. - Stephen Kosonocky (Hot Chips Symposium, 2011)

An x86-64 Core in 32 nm SOI CMOS. - Ravi Jotwani; Sriram Sundaram; Stephen Kosonocky; Alex Schaefer; Victor Andrade; Amy Novak; Sam Naffziger (IEEE J. Solid State Circuits, 2011)

A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs. - Kyle Craig; Yousef Shakhsheer; Sudhanshu Khanna; Saad Arrabi; John C. Lach; Benton H. Calhoun; Stephen Kosonocky (ISLPED, 2012)

Power/performance optimization of many-core processor SoCs. - Stephen Kosonocky; Vladimir Stojanovic; Kees van Berkel 001; Ming-Yang Chao; Tobias Knoll; Joshua Friedrich (ISSCC, 2012)

5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS. - Kevin Gillespie; Harry R. Fair III; Carson Henrion; Ravi Jotwani; Stephen V. Kosonocky; Robert S. Orefice; Donald A. Priore; Jonathan White; Kathryn Wilcox (ISSCC, 2014)

Highlights of the IEEE ISSCC 2014 Processors, Digital, Memory, Biomedical & Next-Generation Systems Technologies, and Imagers, MEMS, Medical & Displays Sessions. - Vivek De; Stephen Kosonocky; Jonathan Chang; Yogesh K. Ramadass; David Stoppa (IEEE J. Solid State Circuits, 2015)

Steamroller Module and Adaptive Clocking System in 28 nm CMOS. - Kathryn Wilcox; Robert Cole; Harry R. Fair III; Kevin Gillespie; Aaron Grenat; Carson Henrion; Ravi Jotwani; Stephen Kosonocky; Benjamin Munger; Samuel Naffziger; Robert S. Orefice; Sanjay Pant; et al. (IEEE J. Solid State Circuits, 2015)

Modeling and implementation of a fully-digital integrated per-core voltage regulation system in a 28nm high performance 64-bit processor. - Ravinder Rachala; Miguel Rodriguez; Stephen Kosonocky; Milos Trajkovic (ISLPED, 2016)

4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management. - Aaron Grenat; Sriram Sundaram; Stephen Kosonocky; Ravinder Rachala; Sriram Sambamurthy; Steven Liepe; Miguel Rodriguez; Tom Burd; Adam Clark; Michael Austin; Samuel Naffziger (ISSCC, 2016)

Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU. - Sriram Sundaram; Sriram Sambamurthy; Michael Austin; Aaron Grenat; Michael Golden; Stephen Kosonocky; Samuel Naffziger (VLSID, 2016)

3.2 Zen: A next-generation high-performance ×86 core. - Teja Singh; Sundar Rangarajan; Deepesh John; Carson Henrion; Shane Southard; Hugh McIntyre; Amy Novak; Stephen Kosonocky; Ravi Jotwani; Alex Schaefer; Edward Chang; Joshua Bell; et al. (ISSCC, 2017)

Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management. - Sriram Sundaram; Aaron Grenat; Samuel Naffziger; Tom Burd; Stephen Kosonocky; Steven Liepe; Ravinder Rachala; Miguel Rodriguez; Michael Austin; Sriram Sambamurthy (IEEE J. Solid State Circuits, 2017)

Zen: An Energy-Efficient High-Performance × 86 Core. - Teja Singh; Alex Schaefer; Sundar Rangarajan; Deepesh John; Carson Henrion; Russell Schreiber; Miguel Rodriguez; Stephen Kosonocky; Samuel Naffziger; Amy Novak (IEEE J. Solid State Circuits, 2018)

A New Era of Tailored Computing. - Mark Papermaster; Stephen Kosonocky; Gabriel H. Loh; Samuel Naffziger (VLSI Circuits, 2021)

Predict; Do not React for Enabling Efficient Fine Grain DVFS in GPUs. - Srikant Bharadwaj; Shomit Das; Kaushik Mazumdar; Bradford M. Beckmann; Stephen Kosonocky (CoRR, 2022)

Predict; Don't React for Enabling Efficient Fine-Grain DVFS in GPUs. - Srikant Bharadwaj; Shomit Das; Kaushik Mazumdar; Bradford M. Beckmann; Stephen Kosonocky (ASPLOS (4), 2023)