Critical issues regarding HPS, a high performance microarchitecture. - Yale N. Patt; Stephen W. Melvin; Wen-mei W. Hwu; Michael Shebanow (MICRO, 1985)

Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers. - Yale N. Patt; Wen-mei W. Hwu; Stephen W. Melvin; Michael Shebanow; Chein Chen; Jiajuin Wei (COMPCON, 1986)

The implementation of Prolog via VAX 8600 microcode. - Jeffrey D. Gee; Stephen W. Melvin; Yale N. Patt (MICRO, 1986)

A microcode-based environment for noninvasive performance analysis. - Stephen W. Melvin; Yale N. Patt (MICRO, 1986)

Run-time generation of HPS microinstructions from a VAX instruction stream. - Yale N. Patt; Stephen W. Melvin; Wen-mei W. Hwu; Michael Shebanow; Chein Chen (MICRO, 1986)

Advantages of Implementing PROLOG by Microprogramming a Host General Purpose Computer. - Jeffrey D. Gee; Stephen W. Melvin; Yale N. Patt (ICLP, 1987)

SPAM: a microcode based tool for tracing operating system events. - Stephen W. Melvin; Yale N. Patt (MICRO, 1987)

On tuning the microarchitecture of an HPS implementation of the VAX. - James E. Wilson; Stephen W. Melvin; Michael Shebanow; Wen-mei W. Hwu; Yale N. Patt (MICRO, 1987)

Aquarius. - Alvin M. Despain; Yale N. Patt; Vason P. Srini; Philip Bitar; William R. Bush; C. Chien; Wayne Citrin; Barry Fagin; Wenwei Hwu; Stephen W. Melvin; Rick McGeer; Ashok Singhal; et al. (SIGARCH Comput. Archit. News, 1987)

Hardware support for large atomic units in dynamically scheduled machines. - Stephen W. Melvin; Michael Shebanow; Yale N. Patt (MICRO, 1988)

The Use of Microcode Instrumentation for Development, Debugging and Tuning of Operating System Kernels. - Stephen W. Melvin; Yale N. Patt (SIGMETRICS, 1988)

Performance benefits of large execution atomic units in dynamically scheduled machines. - Stephen W. Melvin; Yale N. Patt (ICS, 1989)

High Resolution Timing with Low Resolution Clocks and A Microsecond Resolution Timer for Sun Workstations. - Peter B. Danzig; Stephen W. Melvin (ACM SIGOPS Oper. Syst. Rev., 1990)

Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software Techniques. - Stephen W. Melvin; Yale N. Patt (ISCA, 1991)

Enhancing instruction scheduling with a block-structured ISA. - Stephen W. Melvin; Yale N. Patt (Int. J. Parallel Program., 1995)

Handling of packet dependencies: a critical issue for highly parallel network processors. - Stephen W. Melvin; Yale N. Patt (CASES, 2002)

Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor. - Onur Mutlu; Rich Belgard; Thomas R. Gross; Norman P. Jouppi; John L. Hennessy; Steven A. Przybylski; Chris Rowen; Yale N. Patt; Wen-mei W. Hwu; Stephen W. Melvin; Michael Shebanow; Tse-Yu Yeh; et al. (IEEE Micro, 2016)