A digital system modeling philosophy and design language. - Mehmet Baray; Stephen Y. H. Su (DAC, 1971)

The structure and operation of a design language compatible simulator. - Mehmet Baray; Stephen Y. H. Su; Robert L. Carberry (DAC, 1971)

A system modeling language translator. - Stephen Y. H. Su; Mehmet Baray; Robert L. Carberry (DAC, 1971)

Computer-Aided Synthesis or Multiple-Output Multilevel NAND Networks witk Fan-in and Fan-out Constraints. - Stephen Y. H. Su; Chong-Woo Nam (IEEE Trans. Computers, 1971)

A New Approach to the Fault Location of Combinational Circuits. - Stephen Y. H. Su; Yun-Chung Cho (IEEE Trans. Computers, 1972)

Computer Minimization of Multivalued Switching Functions. - Stephen Y. H. Su; Peter T. Cheung (IEEE Trans. Computers, 1972)

The Relationship Between Multivalued Switching Algebra and Boolean Algebra Under Different Definitions of Complement. - Stephen Y. H. Su; Achilles A. Sarris (IEEE Trans. Computers, 1972)

An interactive design automation system. - Stephen Y. H. Su (DAC, 1973)

B73-12 Fault Detection in Digital Circuits. - Stephen Y. H. Su (IEEE Trans. Computers, 1973)

Review of "Fault Diagnosis of Digital Systems" by H. Y. Chang, E. G. Manning, and G. Metze. - Stephen Y. H. Su (IEEE Trans. Syst. Man Cybern., 1973)

Review of "Asynchronous Sequential Switching Circuits" by S. H. Unger. - Stephen Y. H. Su (IEEE Trans. Syst. Man Cybern., 1973)

Speculation on the future of design automation. - Stephen Y. H. Su (DAC, 1974)

A survey of computer hardware description languages in the U.S.A. - Stephen Y. H. Su (Computer, 1974)

Book review of Logic and logic design by B. Girling and H. G. Morning. International Textbook Company Limited 1973. - Stephen Y. H. Su (SIGARCH Comput. Archit. News, 1974)

An introduction to CHDL (computer hardware description languages). - Stephen Y. H. Su (SIGARCH Comput. Archit. News, 1975)

Identification of Multiple Stuck-Type Faults in Combinational Networks. - Melvin A. Breuer; Shih-Jeh Chang; Stephen Y. H. Su (IEEE Trans. Computers, 1976)

An overview of fault-tolerant digital system architecture. - Stephen Y. H. Su; Richard J. Spillman (AFIPS National Computer Conference, 1977)

Logic design automation of diagnosable MOS combinational logic networks. - Yacoub M. El-Ziq; Stephen Y. H. Su (DAC, 1977)

Hardware Description Language Applications: An Introdiction and Prognosis. - Stephen Y. H. Su (Computer, 1977)

Detection of Single, Stuck-Type Faulures in Multivalued Combinational Networks. - Richard J. Spillman; Stephen Y. H. Su (IEEE Trans. Computers, 1977)

A scheme for tolerating faulty data in real-time systems. - John G. Yee; Stephen Y. H. Su (COMPSAC, 1978)

Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results. - Yacoub M. El-Ziq; Stephen Y. H. Su (IEEE Trans. Computers, 1978)

A Continous-Parameter Markov Model and Detection Procedures for Intermittent Faults. - Stephen Y. H. Su; Israel Koren; Yashwant K. Malaiya (IEEE Trans. Computers, 1978)

A survey of methods for intermittent fault analysis. - Yashwant K. Malaiya; Stephen Y. H. Su (MARK, 1979)

Reliability Analysis of N-Modular Redundancy Systems with Intermittent and Permanent Faults. - Israel Koren; Stephen Y. H. Su (IEEE Trans. Computers, 1979)

Detecting bridging and stuck-at faults at input and output pins of standard digital components. - Mark G. Karpovsky; Stephen Y. H. Su (DAC, 1980)

Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines. - Mark G. Karpovsky; Stephen Y. H. Su (IEEE Trans. Computers, 1980)

A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures. - Stephen Y. H. Su; Edgar DuCasse (IEEE Trans. Computers, 1980)

State Diagram Approach for Functional Testing of Control Section. - Chi-Chang Liaw; Stephen Y. H. Su; Yashwant K. Malaiya (ITC, 1981)

Testing Functional Faults in Digital Systems Described by Register Transfer Language. - Stephen Y. H. Su; Yu-I Hsieh (ITC, 1981)

Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits. - Chi-Chang Liaw; Stephen Y. H. Su; Yashwant K. Malaiya (IEEE Trans. Computers, 1981)

Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults. - Yashwant K. Malaiya; Stephen Y. H. Su (IEEE Trans. Computers, 1981)

Testing functional faults in VLSI. - Yinghua Min; Stephen Y. H. Su (DAC, 1982)

A New Fault Model and Testing Technique for CMOS Devices. - Yashwant K. Malaiya; Stephen Y. H. Su (ITC, 1982)

Fault Diagnosis of MOS Combinational Networks. - Yacoub M. El-Ziq; Stephen Y. H. Su (IEEE Trans. Computers, 1982)

A Simplified Algorithm for Testing Microprocessors. - Kewal K. Saluja; Li Shen; Stephen Y. H. Su (ITC, 1983)

IDAS: an integrated design automation system. - Stephen Y. H. Su (AFIPS National Computer Conference, 1984)

Functional testing techniques for digital LSI/VLSI systems. - Stephen Y. H. Su; Tonysheng Lin (DAC, 1984)

VLSI functional testing using critical path traces at hardware description language level. - Li Shen; Stephen Y. H. Su (Fehlertolerierende Rechensysteme, 1984)

Functional Test Generation of Digital LSI/VLSI Systems Using Machine Symbolic Execution Technique. - Tonysheng Lin; Stephen Y. H. Su (ITC, 1984)

VLSI Functional Test Pattern Generation: A Design and Implementation. - Tonysheng Lin; Stephen Y. H. Su (ITC, 1985)

Detecting I/O and Internal Feedback Bridging Faults. - Shiyi Xu; Stephen Y. H. Su (IEEE Trans. Computers, 1985)

The S-Algorithm: A Promising Solution for Systematic Functional Test Generation. - Tonysheng Lin; Stephen Y. H. Su (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985)

Analysis of a Class of Recovery Procedures. - Israel Koren; Zahava Koren; Stephen Y. H. Su (IEEE Trans. Computers, 1986)

Fault Isolation in Grey Systems. - Stephen Y. H. Su; Hede Ma (ITC, 1988)

Designs for Diagnosability and Reliability in VLSI Systems. - Stephen Y. H. Su; Hede Ma (ITC, 1988)

A Functional Testing Method for Microprocessors. - Li Shen; Stephen Y. H. Su (IEEE Trans. Computers, 1988)

Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy. - Mingshien Wang; Michal Cutler; Stephen Y. H. Su (IEEE Trans. Computers, 1989)

Distributed self-diagnosis of VLSI mesh array processors. - Michal Cutler; Stephen Y. H. Su; Mingshien Wang (VTS, 1991)

Self-Diagnosis of Faelures in VLSI Tree Array Processors. - Stephen Y. H. Su; Michal Cutler; Mingshien Wang (IEEE Trans. Computers, 1991)

Fault-Tolerant Array Processors Via Reconfiguration of Two-Level Redundancy Arrays. - Stephen Y. H. Su; Rong Yao (PDPTA, 1997)