Redundant coding of simulated tactile key clicks with audio signals. - Hsiang-Yu Chen; Jaeyoung Park 001; Hong Z. Tan; Steve Dai (HAPTICS, 2010)

Design and Evaluation of Identifiable Key-Click Signals for Mobile Devices. - Hsiang-Yu Chen; Jaeyoung Park 001; Steve Dai; Hong Z. Tan (IEEE Trans. Haptics, 2011)

Design, simulation, and evaluation of imaging oximeters. - Steve Dai; Ye Tian; Joyce E. Farrell (Digital Photography, 2013)

Flushing-Enabled Loop Pipelining for High-Level Synthesis. - Steve Dai; Mingxing Tan; Kecheng Hao; Zhiru Zhang (DAC, 2014)

Multithreaded pipeline synthesis for data-parallel kernels. - Mingxing Tan; Bin Liu 006; Steve Dai; Zhiru Zhang (ICCAD, 2014)

Area-efficient pipelining for FPGA-targeted high-level synthesis. - Ritchie Zhao; Mingxing Tan; Steve Dai; Zhiru Zhang (DAC, 2015)

Mapping-Aware Constrained Scheduling for LUT-Based FPGAs. - Mingxing Tan; Steve Dai; Udit Gupta; Zhiru Zhang (FPGA, 2015)

ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests. - Mingxing Tan; Gai Liu; Ritchie Zhao; Steve Dai; Zhiru Zhang (ICCAD, 2015)

High-level Synthesis for Low-power Design. - Zhiru Zhang; Deming Chen; Steve Dai; Keith A. Campbell (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

Enabling adaptive loop pipelining in high-level synthesis. - Steve Dai; Gai Liu; Ritchie Zhao; Zhiru Zhang (ACSSC, 2017)

Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis. - Steve Dai; Ritchie Zhao; Gai Liu; Shreesha Srinath; Udit Gupta; Christopher Batten; Zhiru Zhang (FPGA, 2017)

Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. - Nitish Kumar Srivastava; Steve Dai; Rajit Manohar; Zhiru Zhang (FPGA, 2017)

Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests. - Gai Liu; Mingxing Tan; Steve Dai; Ritchie Zhao; Zhiru Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. - Steve Dai; Yuan Zhou; Hang Zhang 010; Ecenur Ustun; Evangeline F. Y. Young; Zhiru Zhang (FCCM, 2018)

A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation. - Steve Dai; Gai Liu; Zhiru Zhang (FPGA, 2018)

Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. - Yuan Zhou; Udit Gupta; Steve Dai; Ritchie Zhao; Nitish Kumar Srivastava; Hanchen Jin; Joseph Featherston; Yi-Hsiang Lai; Gai Liu; Gustavo Angarita Velasquez; Wenping Wang; Zhiru Zhang (FPGA, 2018)

High-level synthesis with timing-sensitive information flow enforcement. - Zhenghong Jiang; Steve Dai; G. Edward Suh; Zhiru Zhang (ICCAD, 2018)

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. - Scott Davidson 004; Shaolin Xie; Christopher Torng; Khalid Al-Hawaj; Austin Rovinski; Tutu Ajayi; Luis Vega; Chun Zhao; Ritchie Zhao; Steve Dai; Aporva Amarnath; Bandhav Veluri; et al. (IEEE Micro, 2018)

Improving Scalability of Exact Modulo Scheduling with Specialized Conflict-Driven Learning. - Steve Dai; Zhiru Zhang (DAC, 2019)

MAGNet: A Modular Accelerator Generator for Neural Networks. - Rangharajan Venkatesan; Yakun Sophia Shao; Miaorong Wang; Jason Clemons; Steve Dai; Matthew Fojtik; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Yanqing Zhang 002; Brian Zimmer; et al. (ICCAD, 2019)

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. - Austin Rovinski; Chun Zhao; Khalid Al-Hawaj; Paul Gao 001; Shaolin Xie; Christopher Torng; Scott Davidson 004; Aporva Amarnath; Luis Vega; Bandhav Veluri; Anuj Rao; Tutu Ajayi; et al. (VLSI Circuits, 2019)

Accelerating Chip Design With Machine Learning. - Brucek Khailany; Haoxing Ren; Steve Dai; Saad Godil; Ben Keller; Robert Kirby 001; Alicia Klinefelter; Rangharajan Venkatesan; Yanqing Zhang 002; Bryan Catanzaro; William J. Dally (IEEE Micro, 2020)

Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. - Jacob R. Stevens; Rangharajan Venkatesan; Steve Dai; Brucek Khailany; Anand Raghunathan (DAC, 2021)

Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs. - Dillon Huff; Steve Dai; Pat Hanrahan (FCCM, 2021)

VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. - Steve Dai; Rangharajan Venkatesan; Mark Ren; Brian Zimmer; William J. Dally; Brucek Khailany (MLSys, 2021)

VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. - Steve Dai; Rangharajan Venkatesan; Haoxing Ren; Brian Zimmer; William J. Dally; Brucek Khailany (CoRR, 2021)

Verifying High-Level Latency-Insensitive Designs with Formal Model Checking. - Steve Dai; Alicia Klinefelter; Haoxing Ren; Rangharajan Venkatesan; Ben Keller; Nathaniel Ross Pinckney; Brucek Khailany (CoRR, 2021)

Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update. - Jiawei Zhao; Steve Dai; Rangharajan Venkatesan; Ming-Yu Liu 001; Brucek Khailany; Bill Dally; Anima Anandkumar (CoRR, 2021)

Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. - Charbel Sakr; Steve Dai; Rangharajan Venkatesan; Brian Zimmer; William J. Dally; Brucek Khailany (ICML, 2022)

A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. - Ben Keller; Rangharajan Venkatesan; Steve Dai; Stephen G. Tell; Brian Zimmer; William J. Dally; C. Thomas Gray; Brucek Khailany (VLSI Technology and Circuits, 2022)

LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update. - Jiawei Zhao; Steve Dai; Rangharajan Venkatesan; Brian Zimmer; Mustafa Fayez Ali; Ming-Yu Liu 001; Brucek Khailany; William J. Dally; Anima Anandkumar (IEEE Trans. Computers, 2022)

Efficient Transformer Inference with Statically Structured Sparse Attention. - Steve Dai; Hasan Genc; Rangharajan Venkatesan; Brucek Khailany (DAC, 2023)

Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks. - Nan Wu; Yingjie Li; Cong Hao; Steve Dai; Cunxi Yu; Yuan Xie 001 (DAC, 2023)

A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm. - Ben Keller; Rangharajan Venkatesan; Steve Dai; Stephen G. Tell; Brian Zimmer; Charbel Sakr; William J. Dally; C. Thomas Gray; Brucek Khailany (IEEE J. Solid State Circuits, 2023)

Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and Prospect. - Nan Wu; Yingjie Li; Hang Yang; Hanqiu Chen; Steve Dai; Cong Hao; Cunxi Yu; Yuan Xie 001 (ACM Trans. Design Autom. Electr. Syst., 2024)

SQ-DM: Accelerating Diffusion Models with Aggressive Quantization and Temporal Sparsity. - Zichen Fan; Steve Dai; Rangharajan Venkatesan; Dennis Sylvester; Brucek Khailany (CoRR, 2025)