Incorporating Multi-Chip Module Packaging Constraints into System Design. - Vivek Garg; Steve Lacy; David E. Schimmel; Darrell Stogner; Craig D. Ulmer; D. Scott Wills; Sudhakar Yalamanchili (ED&TC, 1996)

VLSI Architecture: Past, Present, and Future. - William J. Dally; Steve Lacy (ARVLSI, 1999)

In-Datacenter Performance Analysis of a Tensor Processing Unit. - Norman P. Jouppi; Cliff Young; Nishant Patil; David A. Patterson 001; Gaurav Agrawal; Raminder Bajwa; Sarah Bates; Suresh Bhatia; Nan Boden; Al Borchers; Rick Boyle; Pierre-luc Cantin; et al. (ISCA, 2017)

In-Datacenter Performance Analysis of a Tensor Processing Unit. - Norman P. Jouppi; Cliff Young; Nishant Patil; David A. Patterson 001; Gaurav Agrawal; Raminder Bajwa; Sarah Bates; Suresh Bhatia; Nan Boden; Al Borchers; Rick Boyle; Pierre-luc Cantin; et al. (CoRR, 2017)

Exploring the limits of Concurrency in ML Training on Google TPUs. - Sameer Kumar; James Bradbury; Cliff Young; Yu Emma Wang; Anselm Levskaya; Blake A. Hechtman; Dehao Chen; HyoukJoong Lee; Mehmet Deveci; Naveen Kumar; Pankaj Kanwar; Shibo Wang; et al. (CoRR, 2020)

Resiliency at Scale: Managing Google's TPUv4 Machine Learning Supercomputer. - Yazhou Zu; Alireza Ghaffarkhah; Hoang-Vu Dang; Brian Towles; Steven Hand 001; Safeen Huda; Adekunle Bello; Alexander Kolbasov; Arash Rezaei; Dayou Du; Steve Lacy; Hang Wang; et al. (NSDI, 2024)