An Algorithm-Driven Processor Design for Video Compression. - Steve Molloy; Brian Schoner; Avanindra Madisetti; Rajeev Jain; Roy Matic (ICIP (3), 1994)

Techniques for FPGA Implementation of Video Compression Systems. - Brian Schoner; John D. Villasenor; Steve Molloy; Rajeev Jain (FPGA, 1995)

VLSI implementation of a reversible variable length encoder/decoder. - Mario Novell; Steve Molloy (ICASSP, 1999)

Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits. - Yun Zhou; S. C. Song; Halil Kükner; Giuliano Sisto; Sheng Yang; Anita Farokhnejad; Mohamed Naeim; Moritz Brunion; Ji-Yung Lin; Odysseas Zografos; Pieter Weckx; Shashank Ekbote; et al. (VLSI Technology and Circuits, 2024)