Universal Switched-Current Integrator Blocks for SI Filter Design. - Jack L. Chan; Steve S. Chung (ASP-DAC, 1999)

Financial volatility estimation using functional gradient descent algorithm. - Steve S. Chung; Xu-Feng Niu (Model. Assist. Stat. Appl., 2017)

Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F2 and K-means Clustering for Power Reduction. - Keji Zhou; Xiaoyong Xue; Jianguo Yang; Xiaoxin Xu; Hangbing Lv; Mingyu Wang 001; Ming-e Jing; Wenjun Liu; Xiaoyang Zeng; Steve S. Chung; Jing Li; Ming Liu 022 (A-SSCC, 2018)

The Advances of OTP Memory for Embedded Applications in HKMG Generation and Beyond. - Steve S. Chung (ASICON, 2019)

The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and Beyond. - E. R. Hsieh; C. W. Chang; C. C. Chuang; H. W. Chen; Steve S. Chung (VLSI Circuits, 2019)

A Pulsed RTN Transient Measurement Technique: Demonstration on the Understanding of the Switching in Resistance Memory. - E. R. Hsieh; H. W. Cheng; Z. H. Huang; C. H. Chuang; S. P. Yang; Steve S. Chung (IRPS, 2020)

A Reliable Triple-Level Operation of Resistive-Gate Flash Featuring Forming-Free and High Immunity to Sneak Path. - W. Y. Yang; E. R. Hsieh; C. H. Cheng; B. Y. Chen; K. S. Li; Steve S. Chung (IRPS, 2021)

NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnCFE to Break Great Memory Wall with 10 ns of PGM-pulse, 1010 Cycles of Endurance, and Decade Lifetime at 103 °C. - E. R. Hsieh; J. K. Chang; T. Y. Tang; Y. J. Li; C. W. Liang; M. Y. Lin; S. Y. Huang; C. J. Su; J. C. Guo; Steve S. Chung (VLSI Technology and Circuits, 2022)

A World First QLC RRAM: Highly Reliable Resistive-Gate Flash with Record 108 Endurance and Excellent Retention. - M. Y. Li; J. P. Lee; C. H. Liu; J. C. Guo; Steve S. Chung (IRPS, 2023)

First Demonstration of a Design Methodology for Highly Reliable Operation at High Temperature on 128kb 1T1C FeRAM Chip. - Tiancheng Gong; Lihua Xu; Wei Wei; Pengfei Jiang; Peng Yuan; Bowen Nie; Yuanquan Huang; Yuan Wang; Yang Yang; Jianfeng Gao 005; Junfeng Li; Jun Luo; et al. (VLSI Technology and Circuits, 2023)

An Ultra-Low Voltage Auger-Recombination Enhanced Hot Hole Injection Scheme in Implementing a 3 Bits per Cell e-DRAM CIM Macro for Inference Accelerator. - T. C. Kao; M. J. Huang; Y. R. Liu; Y. K. Wang; J. C. Guo; Steve S. Chung (VLSI Technology and Circuits, 2024)

Resistive-Gate RAM: An 1TnR Architecture Feasible for Scaling Beyond 16nm CMOS Generation. - C. H. Sung; M. J. Huang; Y. J. Li; Y. T. Yang; Y. R. Liu; P. H. Shih; J. C. Guo; Steve S. Chung (IRPS, 2025)